Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability

Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops

“…In SRAM cells, the criterion of maximum squares in the mirrored VTCs [15] has been applied to quantify nominal static noise margins [19], which express the stability of the memory element to internal voltage noise during idle mode, read access and write access. SRAM cell stability has been studied in terms of such static noise margins with respect to process variations [26] and to NBTI aging [6]. In [31], the authors present a voltage control technique for improving BTI-degraded SRAM cell stability.…”

Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches

“…The metrics analyzed in this paper are the SNM and the Vmin, since previous works have demonstrated that these are the mostly affected by the BTI aging, and other metrics such as the cell write margin might be negligibly affected by the BTI aging [12]. We also consider a static stress for the SRAM cells in which the cells store the same data for a long period of time.…”

“…We also consider a static stress for the SRAM cells in which the cells store the same data for a long period of time. It has been illustrated that SNM, under static stress varies linearly with V T shifts in FETs [12,13]. Therefore we have used a linear equation to relate the V T shifts to the SNM, in our simulations:…”

Analysis of the relationship between random telegraph signal and negative bias temperature instability

“…negative bias temperature instability (NBTI) [13][14][15], should be considered. With the advent of high-k/metal-gate transistors in SRAM, V min degradation due to positive bias temperature instability (PBTI) will also be significant [16,17].…”