Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs

Abstract

We examine the effectiveness of opportunistic use of reverse body bias (RBB) to reduce leakage power during active operation, burn-in, and standby in 0.18µm single-V t and 0.13µm dual-V t logic process technologies. We investigate its dependencies on channel length, target V t , temperature and technology generation. We show that RBB becomes less effective for leakage reduction at shorter channel lengths and lower V t at both high and room temperatures, especially when target intrinsic leakage currents are high. RBB effectiveness also diminishes with technology scaling primarily because of worsening short-channel effects (SCE), particularly when target V t values are low. We present a model that relates different transistor leakage components to full-chip leakage current, and validate the model through testchip measurements across a range of RBB values.

Thermal-aware clustered microarchitectures

“…Reducing leakage has received the attention of a plethora of studies, as for instance drowsy caches [10], leakage-biased bitlines [13], stacked gates [24], higher V th [16], body bias [17], and others.…”

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

“…The complexity associated with a dual-V TH process is reduced because it has a critical fabrication masking process. Need for additional device fabrication with various threshold voltages are eliminated [71].…”

Active leakage power optimization for FPGAs

“…The body effect is used to raise transistor VTH when high system throughput is not required and the circuit can be slowed down. Such body bias methods can also be used for standby leakage power reduction [9]. Other circuit-level techniques include the use of multi-threshold (MT) CMOS [22,24], in which low-VTH transistors are used in delay critical paths and high-VTH transistors are used in non-critical paths.…”