Introduction:
Advanced low-power designs have been scaled down to the device parameters that increase single-event multi-node upset in memory elements. This degradation of the stability of the memory elements in aerospace applications is due to the high radiation environment and rapid temperature changes.
Method:
Hence, this paper presents a comprehensive treatment model for hardened storage elements with a soft error resulting in multi-node upset. A novel 12T SRAM memory cell configuration has been proposed, analysed, and simulated using Cadence Virtuoso gpdk 45 nm CMOS technology.
Result:
The proposed design counteracts the positive feedback induced due to the charged ion strike, as in past technical literature. The radiation environment has been realized with double exponential current sources, and temperature analysis has been carried out under parametric analysis.
Conclusion:
The novel 12T achieves good stability and remains resilient to bit-flip due to ion strikes for a wider range of voltage when the temperature varies from -50oC to 200oC. Moreover, the proposed structure features a lower susceptibility to single event upset, less write and read time, and reduced area compared to the reported RSP 14T.
This paper presents the implementation of a sense amplifier for a low-power cardiac pacemaker using the Differential Voltage Current Conveyor (DVCC). Two significant aspects of the pacemaker are sensing and pacing. The pulse generator, which is the heart of the pacemaker, consists of a sense amplifier, a logic unit and a timing control unit. The sense amplifier comprises an instrumentation amplifier, a bandpass filter and a comparator that are used to detect the QRS complex wave from the cardiac signal. Based on the output of a sense amplifier, the logic unit and the timing control unit decide whether to pace the heart or not, which achieves the requirement of the demand pacing. In this paper, a novel design of the sense amplifier using a DVCC is proposed, and the simulations are performed using 130-nm TSMC technology. Furthermore, the modes of the pacemaker VVI, DDD and rate-responsive algorithms have been implemented using the structural approach in VHDL by taking into consideration the timing cycles of a pacemaker. The design analysis shows that the proposed model of pacemaker is highly efficient and consumes significantly less energy.
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