Abstract-High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today's system complexity. HLS allows designers to work at a higher-level of abstraction by using a software program to specify the hardware functionality. Additionally, HLS is particularly interesting for designing FPGA circuits, where hardware implementations can be easily refined and replaced in the target device. Recent years have seen much activity in the HLS research community, with a plethora of HLS tool offerings, from both industry and academia. All these tools may have different input languages, perform different internal optimizations, and produce results of different quality, even for the very same input description. Hence, it is challenging to compare their performance and understand which is the best for the hardware to be implemented. We present a comprehensive analysis of recent HLS tools, as well as overview the areas of active interest in the HLS research community. We also present a first-published methodology to evaluate different HLS tools. We use our methodology to compare one commercial and three academic tools on a common set of C benchmarks, aiming at performing an in-depth evaluation in terms of performance and use of resources.

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Abstract-We describe the support within high-level hardware synthesis (HLS) for two standard software parallelization paradigms: Pthreads and OpenMP. Parallel code segments, as specified in the software, are automatically synthesized by our HLS tool into parallel-operating hardware sub-circuits. Both data parallelism and task-level parallelism are supported, as is the combined use of both Pthreads and OpenMP. Moreover, our work also provides automated synthesis for commonly occurring synchronization constructs within the Pthreads/OpenMP library: mutual exclusion (mutex) and barriers. Essentially, our framework allows a software engineer to specify parallelism to an HLS tool using methodologies they are likely to be familiar with. An experimental study considers a variety of parallelization scenarios, including demonstrated speedups of up to 12.9 in circuit wall-clock time for the 16-thread case and area-delay product as low as 12% ( 8 improvement) when using 4 pipelined hardware threads.

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We consider active leakage power dissipation in FPGAs and present a "no cost" approach for active leakage reduction. It is well-known that the leakage power consumed by a digital CMOS circuit depends strongly on the state of its inputs. Our leakage reduction technique leverages a fundamental property of basic FPGA logic elements (look-uptables) that allows a logic signal in an FPGA design to be interchanged with its complemented form without any area or delay penalty. We apply this property to select polarities for logic signals so that FPGA hardware structures spend the majority of time in low leakage states. In an experimental study, we optimize active leakage power in circuits mapped into a state-of-the-art 90nm commercial FPGA. Results show that the proposed approach reduces active leakage by 25%, on average.

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Abstract-We describe new multi-ported cache designs suitable for use in FPGA-based processor/parallel-accelerator systems, and evaluate their impact on application performance and area. The baseline system comprises a MIPS soft processor and custom hardware accelerators with a shared memory architecture: on-FPGA L1 cache backed by off-chip DDR2 SDRAM. Within this general system model, we evaluate traditional cache design parameters (cache size, line size, associativity). In the parallel accelerator context, we examine the impact of the cache design and its interface. Specifically, we look at how the number of cache ports affects performance when multiple hardware accelerators operate (and access memory) in parallel, and evaluate two different hardware implementations of multi-ported caches using: 1) multi-pumping, and 2) a recently-published approach based on the concept of a livevalue table. Results show that application performance depends strongly on the cache interface and architecture: for a system with 6 accelerators, depending on the cache design, speedup swings from 0.73× to 6.14×, on average, relative to a baseline sequential system (with a single accelerator and a direct-mapped, 2KB cache with 32B lines). Considering both performance and area, the best architecture is found to be a 4-port multi-pump direct-mapped cache with a 16KB cache size and a 128B line size.

Electron ic En g in eerin g , Im perial C olleg e L on d on , U K B r a n don B lodg et, J a m es A n der s on Pa tr ick L y s a g h t X ilin x , In c., 2 1 0 0 L og ic Driv e, S an J os e, C A 9 5 1 2 4 , U S A T ob ia s B eck er U n iv ers ität K arls ru h e (T H ), K ais ers traß e 1 2 -7 6 1 3 1 K arls ru h e, G erm an y ABSTRACT Modular systems implemented on Field-Programmable G ate A rrays c an benefi t from being able to load and unload modules at run-time, a c onc ept th at is of muc h interest in th e researc h c ommunity. W h ile dynamic partial rec onfi guration is possible in V irtex series and S partan series FPG A s, th e c onfi guration arc h itec ture of th ese dev ic es is not amenable to modular rec onfi guration, a limitation w h ic h h as relegated researc h to th eoretic al or c ompromised resourc e alloc ation models. In th is paper tw o meth ods for implementing modular dynamic rec onfi guration in V irtex FPG A s are c ompared and c ontrasted. T h e fi rst meth od offers simplic ity and fast rec onfi guration times, but limits th e geometry and c onnectiv ity of th e system. T h e sec ond meth od, rec ently dev eloped by th e auth ors, enables modules to be alloc ated arbitrary areas of th e FPG A , bridging th e gap betw een th eory and reality and unloc k ing th e latent potential of partial rec onfi guration. T h e later meth od h as been demonstrated in th ree applic ations. . I N TRO D U CTI O NT h e transistor density of Field Programmable G ate A rrays h as reac h ed a lev el w h ere an entire system may be implemented w ith in a single dev ic e. A c omplex system is generally c omposed from many func tionally disc rete modules, w h ic h are c onnec ted to form a c oh erent w h ole. In some c ases w h ere th e req uirements on th e system are time-v ariant, not all modules need to operate c onc urrently. A n unused module resident in th e FPG A w ill w aste pow er, area and c ost, and th erefore it w ould be adv antageous if modules are able to be loaded only w h en an applic ation is inv ok ed and remov ed again onc e th e applic ation h as terminated.T h ere h as been a large amount of researc h in th e area of dynamic modular systems in FPG A s [1 , 2 , 3 , 4 , 5 ]. T h ese are predic ated on th e property of dynamic partial rec onfi guration, h ow ev er module-based rec onfi guration h as not been intrinsic ally supported in FPG A s sinc e th e demise of th e * The authors wish to thank Jean Belzile, Normand Leclerc, Pierre-A ndré M eunier and D av id R ob erg e from IS R Technolog ies for their inv aluab le contrib utions, and also Peter C heung for his critiq ue of this p ap er.X ilinx 6 2 0 0 series. W h ile th e V irtex and S partan series of FPG A s are partially rec onfi gurable, th e essentially linear organisation of th e c onfi guration memory is not amenable to th e implementation of module-based systems w ith tw odimensional fl oorplans. A s a result researc h h as tended to be eith er th eoretic al, or sev erely c irc umsc ribed, typic ally by reduc ing th e resour...