From software threads to parallel hardware in high-level synthesis for FPGAs

Abstract

Abstract-We describe the support within high-level hardware synthesis (HLS) for two standard software parallelization paradigms: Pthreads and OpenMP. Parallel code segments, as specified in the software, are automatically synthesized by our HLS tool into parallel-operating hardware sub-circuits. Both data parallelism and task-level parallelism are supported, as is the combined use of both Pthreads and OpenMP. Moreover, our work also provides automated synthesis for commonly occurring synchronization constructs within the Pthreads/OpenMP library: mutual exclusion (mutex) and barriers. Essentially, our framework allows a software engineer to specify parallelism to an HLS tool using methodologies they are likely to be familiar with. An experimental study considers a variety of parallelization scenarios, including demonstrated speedups of up to 12.9 in circuit wall-clock time for the 16-thread case and area-delay product as low as 12% ( 8 improvement) when using 4 pipelined hardware threads.

Exploiting vectorization in high level synthesis of nested irregular loops

“…The proposed methodology has been verified on a set of parallel benchmarks distributed with Legup [8]. In OpenMP benchmarks each #pragma omp for has been replaced with #pragma omp simd, while pthread benchmarks have to be re-factorized to replace pthread parallelism with #pragma omp simd.…”

“…The synthesis of Blackschoels on the Stratix V with P = 3,4,8 was not been possible because the device does not contain enough DSPs to implement the vectorized version of the benchmarks. The area results refer only to the synthesized accelerators since the produced parallel hardware architectures, differently from the ones presented in [8], do not require any external processor nor external controller to be integrated in a system. Memory utilization has not been reported since it is independent from the degree of parallelism.…”

“…The scheduling of the memory accesses is fully deterministic and it is completely computed at this time. For this reason, the proposed methodology does not require complex memory controller to arbitrate the parallel memory accesses as in [8], [10], [9]. Moreover, in principle it is possible to exploit the proposed methodology even if the rest of the flow does not support vectorization at all.…”

“…This code is then provided as input to AutoPilot which performs the actual synthesis producing a multi accelerators system. In a similar way, Choi et al [8] proposed the automatic synthesis of applications already parallelized, but they start from applications exploiting pthreads and OpenMP API. In this case, the methodology directly produces parallel hardware implementations of the loops which have been annotated with #pragma omp for (they are DoAll loops with compile time known number of iterations).…”

“…The intermediate representation must have the properties which have been described in Section 3: SSA form and absence of complex instructions. Note that most of the state of the art High Level Synthesis tools (e.g., [8], [9], [20]) already adopt an internal intermediate representation which satisfies these requirements.…”