Modular partial reconfiguration in virtex FPGAs

Abstract

Electron ic En g in eerin g , Im perial C olleg e L on d on , U K B r a n don B lodg et, J a m es A n der s on Pa tr ick L y s a g h t X ilin x , In c., 2 1 0 0 L og ic Driv e, S an J os e, C A 9 5 1 2 4 , U S A T ob ia s B eck er U n iv ers ität K arls ru h e (T H ), K ais ers traß e 1 2 -7 6 1 3 1 K arls ru h e, G erm an y ABSTRACT Modular systems implemented on Field-Programmable G ate A rrays c an benefi t from being able to load and unload modules at run-time, a c onc ept th at is of muc h interest in th e researc h c ommunity. W h ile dynamic partial rec onfi guration is possible in V irtex series and S partan series FPG A s, th e c onfi guration arc h itec ture of th ese dev ic es is not amenable to modular rec onfi guration, a limitation w h ic h h as relegated researc h to th eoretic al or c ompromised resourc e alloc ation models. In th is paper tw o meth ods for implementing modular dynamic rec onfi guration in V irtex FPG A s are c ompared and c ontrasted. T h e fi rst meth od offers simplic ity and fast rec onfi guration times, but limits th e geometry and c onnectiv ity of th e system. T h e sec ond meth od, rec ently dev eloped by th e auth ors, enables modules to be alloc ated arbitrary areas of th e FPG A , bridging th e gap betw een th eory and reality and unloc k ing th e latent potential of partial rec onfi guration. T h e later meth od h as been demonstrated in th ree applic ations. . I N TRO D U CTI O NT h e transistor density of Field Programmable G ate A rrays h as reac h ed a lev el w h ere an entire system may be implemented w ith in a single dev ic e. A c omplex system is generally c omposed from many func tionally disc rete modules, w h ic h are c onnec ted to form a c oh erent w h ole. In some c ases w h ere th e req uirements on th e system are time-v ariant, not all modules need to operate c onc urrently. A n unused module resident in th e FPG A w ill w aste pow er, area and c ost, and th erefore it w ould be adv antageous if modules are able to be loaded only w h en an applic ation is inv ok ed and remov ed again onc e th e applic ation h as terminated.T h ere h as been a large amount of researc h in th e area of dynamic modular systems in FPG A s [1 , 2 , 3 , 4 , 5 ]. T h ese are predic ated on th e property of dynamic partial rec onfi guration, h ow ev er module-based rec onfi guration h as not been intrinsic ally supported in FPG A s sinc e th e demise of th e * The authors wish to thank Jean Belzile, Normand Leclerc, Pierre-A ndré M eunier and D av id R ob erg e from IS R Technolog ies for their inv aluab le contrib utions, and also Peter C heung for his critiq ue of this p ap er.X ilinx 6 2 0 0 series. W h ile th e V irtex and S partan series of FPG A s are partially rec onfi gurable, th e essentially linear organisation of th e c onfi guration memory is not amenable to th e implementation of module-based systems w ith tw odimensional fl oorplans. A s a result researc h h as tended to be eith er th eoretic al, or sev erely c irc umsc ribed, typic ally by reduc ing th e resour...

Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation

“…In 2006, Xilinx introduced the Early Access Partial Reconfiguration Design Flow (Xilinx 2006) that integrated concepts introduced earlier in works such as (Sedcole et al 2005) and (Becker et al 2003). Researches such as (Bayar & Yurdakul 2008) and (Paulsson et al 2007) focus on implementing softcore internal configuration cores on Xilinx FPGAs such as Spartan-3, that do not have the hardware internal reconfiguration cores, for effective implementation of PDR.…”

“…(Sedcole et al 2005) presented an effective modular approach for 2-dimensional reconfigurable modules. Similarly, (Becker et al 2003) implemented 1-dimensional modular reconfiguration using a horizontal slice based bus macro to connect the static and partially dynamic regions.…”

Exploiting dynamic reconfiguration of platform FPGAs: implementation issues

“…Several ways to address the problem have been reported [11,6,10,12]. One way is to have a tool like BitLinker [12], that is capable of ensuring that the configuration bitstream is complete (i.e., not "differential").…”

“…Other systems based on dynamically reconfigurable platform FPGAs have been described in the literature (see, for instance, [13,2,1,11]). Aspects of the 32-bit design used for this work have been presented in [5].…”

Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System

“…Xilinx Virtex, Virtex-2, and Virtex-2 Pro devices can be reconfigured in a columnbased way [4]. The authors of [5] developed the "merge dynamic reconfiguration" technique in the Virtex-4 architecture. In this paper, we present our approach to harness the dynamic partial reconfiguration technique in a reconfigurable blade.…”