Erratic fluctuations of sram cache vmin at the 90nm process technology node

Agostinelli, M.; Hicks, J.; Xu, Jianzhong; Woolery, B.; Mistry, K.; Zhang, K.; Jacobs, Steve; Jopling, J.; Yang, Wenxing; Lee, B.; Raz, T.; Mehalel, Moty; Kolar, Pramod; Wang, Y.; Sandford, J.; Pivin, D.; Peterson, Christopher W.; DiBattista, Mike; Pae, Sangwoo; Jones, Marshall; Johnson, Stephen C.; Subramanian, G. Ganesan

doi:10.1109/iedm.2005.1609436

Cited by 91 publications

(65 citation statements)

References 4 publications

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“…Since ∆V th is inversely proportional to the device area, highly integrated digital devices are assumed to be seriously affected by RTN. For instance, Figure 42 illustrates the measurement data from a 90nm SRAM design [83]. The minimum supply voltage (V ccmin ), which is highly sensitive to device threshold voltage, exhibits a similar pattern in the time domain as that of RTS.…”

Section: 2mentioning

confidence: 99%

Monte Carlo Device Simulations

Raleva¹,

Shaik

Hathwar

et al. 2011

Applications of Monte Carlo Method in Science and Engineering

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As semiconductor devices are scaled into nanoscale regime, first velocity saturation starts to limit the carrier mobility due to pronounced intervalley scattering, and when the device dimensions are scaled to 100 nm and below, velocity overshoot (which is a positive effect) starts to dominate the device behavior leading to larger ON-state currents. Alongside with the developments in the semiconductor nanotechnology, in recent years there has been significant progress in physical based modeling of semiconductor devices. First, for devices for which gradual channel approximation can not be used due to the two-dimensional nature of the electrostatic potential and the electric fields driving the carriers from source to drain, drift-diffusion models have been exploited. These models are valid, in general, for large devices in which the fields are not that high so that there is no degradation of the mobility due to the electric field. The validity of the drift-diffusion models can be extended to take into account the velocity saturation effect with the introduction of field-dependent mobility and diffusion coefficients. When velocity overshoot becomes important, drift diffusion model is no longer valid and hydrodynamic model must be used. The hydrodynamic model has been the workhorse for technology development and several high-end commercial device simulators have appeared including Silvaco, Synopsys, Crosslight, etc. The advantages of the hydrodynamic model are that it allows quick simulation runs but the problem is that the amount of the velocity overshoot depends upon the choice of the energy relaxation time. The smaller is the device, the larger is the deviation when using the same set of energy relaxation times. A standard way in calculating the energy relaxation times is to use bulk Monte Carlo simulations. However, the energy relaxation times are material, device geometry and doping dependent parameters, so their determination ahead of time is not possible. To avoid the problem of the proper choice of the energy relaxation times, a direct solution of the Boltzmann Transport Equation (BTE) using the Monte Carlo method is the best method of choice. That is why the focus of this review paper is on explaining basic Monte Carlo device simulator and then the focus will be shifted on the inclusion of various higher order effects that explain particular physical phenomena or processes.The Monte Carlo book chapter is organized as follows. First, the idea behind the Monte Carlo technique is outlined by revoking the path integral method for the solution of the BTE. This approach naturally leads to the free-flight-scatter sequence that is used in solving the BTE using the Monte Carlo method. Various scattering mechanisms relevant for different materials are given to completely specify the collision integral in the BTE. A discussion followed with the presentation of a generic flow-chart for implementing bulk Monte Carlo code is presented. Note that bulk Monte Carlo approach is suitable for the characterization of ma...

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Section: 2mentioning

confidence: 99%

Monte Carlo Device Simulations

Raleva¹,

Shaik

Hathwar

et al. 2011

Applications of Monte Carlo Method in Science and Engineering

View full text Add to dashboard Cite

show abstract

“…Alternatively, the program can be executed serially twice in a single-threaded core, but this may roughly double execution time. Either way, errors produced due to permanent and intermittent faults (e.g., those caused due to degradation or "telegraph radio noise" [4]) are very likely to repeat in both executions, thus remaining undetected. Instead, space replication requires the execution of the program in two distinct cores, typically simultaneously.…”

Section: Error Detection For Automotive Safety-critical Applicationsmentioning

confidence: 99%

“…Typically, CRTES industry relies on error detection and correction codes for memory devices such as main memory and caches [14] and space redundancy for the remaining devices as this allows to deal with any type of error [25], [19], [17], [20], [34]. Note that solutions based on time redundancy such as redundant multithreaded (RMT) processors [31], [27] are typically dismissed as they do not provide guarantees to detect faults due to degradation and "telegraph radio noise" [4].…”

Section: Timely Recovery With Livementioning

confidence: 99%

Timely Error Detection for Effective Recovery in Light-Lockstep Automotive Systems

Hernández

Abella

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Safety-relevant systems in the automotive domain often implement features such as lockstep execution for error detection, and reset and reexecution for error correction. Lightlockstep has already been adopted in some such systems due to its relatively low implementation cost given that it does not require deep changes into non-lockstep hardware. Instead, as only off-core activities (i.e. data/addresses sent) need to be compared across different cores, light-lockstep designs are lowly intrusive. This approach has been proven sufficient to guarantee functional correctness of the system in the presence of errors in the cores, in particular in relation with certification against safety standards such as ISO26262 in the automotive domain. However, error detection in light-lockstep systems may occur long after the error actually occurs, thus jeopardising timing guarantees, which are as critical as functional ones in hard real-time systems.In this paper we analyse the timing behaviour of errors due to transient and permanent faults in light-lockstep systems. Our results show that the time elapsed until an error is detected can be inordenately large, especially for permanent faults. Based on this observation and building upon the specific characteristics of light-lockstep systems, we propose LiVe (Lightly Verbose), a new mechanism to enforce the early detection of errors, due to both transient and permanent faults, thus enabling the computation of tight error detection timing bounds. We also analyse how existing mechanisms for error recovery in multicore systems increase their effectiveness when light-lockstep operates in LiVe mode in the context of mixed-criticality workloads.

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“…Large-scale characterization techniques, involving characterization of SRAM cells in-situ within the array, provide a better estimate of the impact of these systematic effects on SRAM performance. Thus, SRAM designers continue to rely on collecting distributions of bitline read currents [37] and minimum operating voltage (V MIN ) [38][39] to gauge SRAM read stability and writeability in large functional SRAM arrays.…”

Section: Sram Characterizationmentioning

confidence: 99%

Technology variability from a design perspective

Nikolić

Giraud

Guo

et al. 2010

IEEE Custom Integrated Circuits Conference 2010

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Increased variability in semiconductor process technology and devices requires added margins in the design to guarantee the desired yield. Variability is characterized with respect to the distribution of its components, its spatial and temporal characteristics and its impact on specific circuit topologies. Approaches to variability characterization and modeling for digital logic and SRAM are reviewed in this paper. Transistor and ring oscillator arrays are designed to isolate specific systematic and random variability components in the design. Distributions of SRAM design margins are measured by padded-out cells and minimum operating voltages for the entire array. Correlations between various components of variability are essential for adding appropriate margins to the design.

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Erratic fluctuations of sram cache vmin at the 90nm process technology node

Cited by 91 publications

References 4 publications

Monte Carlo Device Simulations

Monte Carlo Device Simulations

Timely Error Detection for Effective Recovery in Light-Lockstep Automotive Systems

Technology variability from a design perspective

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