drain. In contrast, if the applied vohage attracts the channel charge and repels t & source and drain charge, no condwtinglayer between the source and drain em form, and the transistor is "off." The transistor thus acts as a digital switch that is turned on or off by app-a voltage to -&-chips. For more than 30 yeas, the switching (2). At the same #he, the ttital amaunt of charge in the source, drain, aud channel regions must not decrease in ordg to mained by locally adding dopant atoms to the The authors are at the Chemie 'I, U n i a1 propertics can rcsult froin colllbinillg distributioils. Olefin conlonomers arc versitat Ulm, Albert-Einstein-Allee 1 I, D-89069 Ulm,petri,~ehmusechemie,uni.ulm,de; the rational desigil of organometallic cata-used to alter the crystallinit) of the poly-
We investigate scaling challenges and outline device design requirements needed to support high performance-low power planar CMOS transistor structures with physical gate lengths ( L G A~) below 50nm. This work uses a combination of simulation results, experimental data and critical analysis of published data. A realistic assessment of gate oxide thickness scaling and maximum tolerable oxide leakage is provided. We conclude that the commonly accepted upper limit of lA/cm2 for gate leakage is overly pessimistic and that leakage values of up to 100A/cm2 are deemed acceptable for future logic technology generations. Unique channel mobility and junction edge leakage degradation mechanisms, which become prominent at 50nmLGAm dimensions, are highlighted using quantitative analysis. Source-drain extension (SDE) profile design requirements to simultaneously minimize short channel effects (SCE) and achieve low parasitic resistance for sub-50nmLGAm transistors are described for the first time.Scaling Issues & Device Requirements Table 1 summarizes key transistor scaling requirements for 70-180nm logic technology nodes. The projections are based on extrapolating results from 180nm logic technology node published by this group and other industry leaders [l-31. Given limited room for further VTH scalability due to static power considerations, the supply voltage is expected to scale by only 0 . 8~ per generation to maintain an acceptable gate overdrive (Fig. I). Electrical oxide thickness is projected to scale by 0 . 8~ per generation to maintain reliability [constant VDflox(e)]. SDE depth and under-diffusion are projected to scale by 0 . 7~ per generation to control SCE and support LGATE. Channel doping projections are commensurate with gate oxide scaling requirements. A comprehensive analysis of scaling issues and device design requirements is presented next. (a) Gate Oxide Scaling: Fig. 2 shows gate oxide leakage (Jox) dependence on physical TOX-EFF for pure Si02 and nitrided-Si02 gates. Pure Si02 leakage data is extracted from Ref.[4] and incorporates VDD scaling with Tox from Table 1. More than lox JoX reduction relative to pure oxide is observed at the same physical TOX-EFF for optimized nitrided-Si02 [3]. This data point is used together with the Jox vs. TOX-EFF slope already obtained for pure oxide to project gate leakage values for future nodes for devices with nitrided-Si02 gate. Fig. 3 shows computed transistor sub-threshold (IoFF) and IGATE components of static leakage at 25" C and 100°C vs.LGATE for an inverter with FO=3. Leakage calculations assume nitrided-Si02 and use the IOFF and Tox parameters listed in Table 1. Experimentally measured temperature acceleration factors are used to determine IoFF at 100°C. Fig. 4 shows that IGATE is 7x lower than IoFF at 100°C (product operating temperature) at the 50nm LGATE node, and has a Jox of -100A/cm2. Circuit simulations using IoFF values from Table 1 and 100A/cmZ gate leakage, show acceptable functionality and noise margin for both static and domino circuits at the 50n...
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