Positive-bias temperature instability (PBTI) of GaN MOSFETs

Abstract

-We have investigated the stability of the gate stack of GaN n-MOSFETs under positive gate stress. Devices with a gate dielectric that consists of pure SiO2 or a composite SiO2/Al2O3 bilayer were studied. Our research has targeted the evolution of threshold voltage (VT), subthreshold swing (S) and transconductance (gm) after positive gate voltage stress of different duration at different voltages and temperatures. We have also examined the recovery process after the stress is removed. We have observed positive VT shift (∆VT) in both gate dielectrics under positive gate stress. In devices with a SiO2 gate oxide, we have found that ∆VT is caused by a combination of electron trapping in pre-existing oxide traps and interface trap generation. In devices with a composite SiO2/Al2O3 gate oxide, on the other hand, ∆VT is due to electron trapping in pre-existing oxide traps and generation of near interface oxide traps.

Gate dielectric reliability and instability in GaN metal-insulator-semiconductor high-electron-mobility transistors for power electronics

“…Indeed, if, as suggested in Ref. 39, we plot t 1BD with its corresponding PBD time, t PBD , as shown in the inset of Fig. 3, we see that the two are independent of one another.…”

“…Not described here are stress-and-measure experiments that aim to understand the impact that the high electric field stress has on the device transfer characteristics. The transient instabilities by which GaN MIS-HEMTs are plagued 17,39 make this understanding more difficult. A methodology to address these issues and develop suitable experimental techniques has been described elsewhere.…”

Bias Temperature Instability of Normally‐Off GaN MIS‐FET with Low‐Pressure Chemical Vapor Deposition SiNx Gate Dielectric

“…Even at a high temperature of 150 °C, the shift of V TH is only slightly increased to 0.9 V (Figure (a)) and 0.7 V (Figure (a)) for positive and negative gate bias stress, respectively. The E‐mode LPCVD‐SiN x MIS‐FET with a PECVD‐SiN x interfacial layer shows greatly improved V TH stability compared with that reported in SiO 2 /GaN and Al 2 O 3 /GaN MOS‐FETs …”

“…Generation of new defects during the BTI stress is negligible in the MIS‐FET with PECVD‐SiN x interlayer. Under positive gate bias, electron trapping in pre‐existing interface/border trap states is responsible for the positive V TH shifts . The smaller V TH shift of the LPCVD‐SiN x /PECVD‐SiN x /GaN MIS‐FET than that of the MIS‐FET without interlayer indicates that there is reduced electron trapping, which results from the enhanced interface quality with lower interface/border trap density.…”

“…In applications, a positive gate bias V GS is always needed for a large gate overdrive ( V GS − V TH ) to fully turn‐on the devices. Thus, the V TH stability under forward gate bias is one of the critical reliability issues in the normally‐off MIS‐FETs . On the other hand, under negative bias stress, electron detrapping may result in negative V TH shifts, which will lead to the false turn‐on of MIS‐FETs.…”