2012 IEEE International Interconnect Technology Conference 2012
DOI: 10.1109/iitc.2012.6251663
|View full text |Cite
|
Sign up to set email alerts
|

Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1

Citation Types

0
22
0

Year Published

2013
2013
2024
2024

Publication Types

Select...
6
2
1

Relationship

1
8

Authors

Journals

citations
Cited by 38 publications
(22 citation statements)
references
References 3 publications
0
22
0
Order By: Relevance
“…The ∆V th s in the various process corners are properly assumed to be between 35 and 50 mV according to process corners [7]. In addition, the interconnect capacitance is set to 0.16fF/μm [16], and the gate-to-source or drain capacitance and junction capacitance in source or drain are set to 0.252 fF/μm [17] and 0.72 fF/μm 2 [18], respectively.…”
Section: A Simulation Setupmentioning
confidence: 99%
“…The ∆V th s in the various process corners are properly assumed to be between 35 and 50 mV according to process corners [7]. In addition, the interconnect capacitance is set to 0.16fF/μm [16], and the gate-to-source or drain capacitance and junction capacitance in source or drain are set to 0.252 fF/μm [17] and 0.72 fF/μm 2 [18], respectively.…”
Section: A Simulation Setupmentioning
confidence: 99%
“…In this work backside laser exposure is used because the interconnect layers present in Intel's 22nm/32nm technology nodes [10] are very dense. For this reason front side optical injection is not viable on the current CMOS fully integrated manufacturing processes .…”
Section: B Laser Datamentioning
confidence: 99%
“…To reduce the effective capacitance (k eff ) in the copper backend interconnection, low-k etch-stop/ dielectric barrier materials such as silicon carbonitride (SiC x N y ) (k = 4.5-5.5) [2] have been introduced in 45 nm nodes and beyond, following the implementation of low-k inter-layer dielectric (ILD) materials such as carbon-doped oxide and ultra-low-k dielectrics [3] and the scaling of their thickness [4,5]. Silicon carbonitride films have been typically prepared using plasma-enhanced chemical vapor deposition (PECVD) of multi-precursors such as SiH 4 + NH 3 (or N 2 ) + CH 4 [6,7] and SiH(CH 3 ) 3 + NH 3 [8].…”
Section: Introductionmentioning
confidence: 99%
“…To reduce the effective capacitance (k eff ) in the copper backend interconnection, low-k etch-stop/ dielectric barrier materials such as silicon carbonitride (SiC x N y ) (k = 4.5-5.5) [2] have been introduced in 45 nm nodes and beyond, following the implementation of low-k inter-layer dielectric (ILD) materials such as carbon-doped oxide and ultra-low-k dielectrics [3] and the scaling of their thickness [4,5]. Silicon carbonitride films have been typically prepared using plasma-enhanced chemical vapor deposition (PECVD) of multi-precursors such as SiH 4 + NH 3 (or N 2 ) + CH 4 [6,7] and SiH(CH 3 ) 3 + NH 3 [8]. Recently, single source precursors such as hexamethyldisilazane (HMDS) [9,10], and BASICN TM [11] have been examined for use in low-k SiC x N y applications, because compared with multi-precursors, single source precursors retain higher C content to achieve lower polarizability and improved etch selectivity.…”
Section: Introductionmentioning
confidence: 99%