D. Ingerly scite author profile

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D. Ingerly

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing

A 14 nm SoC platform technology featuring 2<sup>nd</sup> generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um<sup>2</sup> SRAM cells, optimized for low power, high performance and high density SoC products

Foveros: 3D Integration and the use of Face-to-Face Chip Stacking for Logic Devices

Performance enhancement for 14nm high volume manufacturing microprocessor and system on a chip processes

Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing

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