A 14 nm SoC platform technology featuring 2&lt;sup&gt;nd&lt;/sup&gt; generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um&lt;sup&gt;2&lt;/sup&gt; SRAM cells, optimized for low power, high performance and high density SoC products

Jan, C.-H.; Al-Amoody, F.; Chang, Hsin-Wen; Chang, Tsung-Chou; Chen, Y.-W.; Dias, N. L.; Hafez, W.; Ingerly, D.; Jang, M.; Karl, Eric; Shi, Song; Komeyli, K.; Kilambi, H.; Kumar, Arun; Byon, Kumhyo; Lee, C.-G.; Lee, J.; Leo, Tulus; Liu, P.-C.; Nidhi, Nitin; Olac-vaw, Roman; Petersburg, Cole; Phoa, K.; Prasad, C.; Quincy, C.; Ramaswamy, R.; Rana, T. K.; Rockford, L.; Subramaniam, Anand Bala; Tsai, C.; Vandervoorn, P.; Yang, L.; Zainuddin, Abu; Bai, P.

doi:10.1109/vlsic.2015.7231380

Cited by 25 publications

(19 citation statements)

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“…To evaluate each SRAM cell, Monte Carlo simulations were performed with varying V th using a BSIM-CMG FinFET model [16]. This model card was fitted to achieve the characteristics of the industrial technical parameters in 14 nm FinFET technology, as listed in Table I [17]. The FinFETs have two major sources of variability, work function variation and line edge roughness [18], which can be modeled by the variation in V th .…”

Section: Simulation Results and Comparisonmentioning

confidence: 99%

Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology

Yang

Jeong

Song

et al. 2016

IEEE Trans. Circuits Syst. I

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Although near-threshold voltage (NTV) operation is an attractive means of achieving high energy efficiency, it can degrade the circuit stability of static random access memory (SRAM) cells. This paper proposes an NTV 7T SRAM cell in a 14 nm FinFET technology to eliminate read disturbance by disconnecting the path from the bit-line to the cross-coupled inverter pair using the transmission gate. In the proposed 7T SRAM cell, the halfselect issue is resolved, meaning that no write-back operation is required. A folded-column structure is applied to the proposed 7T SRAM cell to reduce the read access time and energy consumption. To reduce the standby power, the proposed 7T SRAM cell uses only a single bit-line for both read and write operations. To achieve proper "1" writing operation with a single bit-line, a two-phase approach is proposed. Compared to the conventional 8T SRAM cell, the proposed 7T SRAM cell improves the read access time, energy, and standby power by 13%, 42%, and 23%, respectively, with a 3% smaller cell area.Index Terms-FinFET, low-power design, near-threshold operation, single bit-line structure, SRAM cell. 1549-8328

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Section: Simulation Results and Comparisonmentioning

confidence: 99%

Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology

Yang

Jeong

Song

et al. 2016

IEEE Trans. Circuits Syst. I

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“…Fins are usually defined by SADP [26]. Fin etching in bulk silicon has to be controlled by a timer Figure 2 [21][22][23][24].…”

Section: Precise and Uniform Fin Formationmentioning

confidence: 99%

The Challenges of Advanced CMOS Process from 2D to 3D

Radamson

Zhang

et al. 2017

Applied Sciences

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Abstract:The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

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“…entries, even causing the depletion of the remaining IPv4 address space and leading to the advent of an IPv6 protocol with a quadrupled need for address look-up (AL) requirements [5]. This increasing need for faster routing functionalities, including AL, which also requires fast hardware memories to perform fast look-up of the packet's destination address immediately upon its arrival and across the forwarding information base (FIB) of the router.On the path to speeding up hardware memory and lower latency times when fetching data, state-of-the-art highly performing electronic static random access memory (RAM) cell technology has managed to achieve operation up to 5 GHz [6][7][8]. However, RAMs are inherently limited in fast AL as, owing to the address-based fetching of data, they would require multiple sequential random access to the memory and consecutive searches of the desired content.…”

mentioning

confidence: 99%

“…On the path to speeding up hardware memory and lower latency times when fetching data, state-of-the-art highly performing electronic static random access memory (RAM) cell technology has managed to achieve operation up to 5 GHz [6][7][8]. However, RAMs are inherently limited in fast AL as, owing to the address-based fetching of data, they would require multiple sequential random access to the memory and consecutive searches of the desired content.…”

mentioning

confidence: 99%

Optical memory architectures for fast routing address look-up (AL) table operation

et al. 2019

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Today, the increasing demand for fast routing processes has turned the address look-up (AL) operation into one of the main critical performance operations in modern optical networks, since it conventionally relies on slow-performing AL tables. Specifically, AL memory tables are comprised of content addressable memories (CAMs) for storing a known route of the forwarding information base of the router, and random access memories (RAMs) for storing the respective output port for this route. They thus allow for a one-cycle search operation of a packet's destination address, yet they typically operate at speeds well below 1 GHz, in contrast with the vastly increasing optical line rates. In this paper, we present our overall vision towards light-based optical AL memory functionalities that may facilitate faster router AL operations, as the means to replace slow-performing electronic counterparts. In order to achieve this, we report on the development of a novel optical RAM cell architecture that performs for the first time with a speed of up to 10 Gb s −1 , as well as our latest works on multi-bit 10 Gb s −1 optical CAM cell architectures. Specifically, the proposed optical RAM cell exploits a semiconductor optical amplifier-Mach-Zehnder interferometer in a push-pull configuration and deep saturation regime, doubling the speed of prior optical RAM cell configurations. Errorfree write/read operation is demonstrated with a peak power penalty of 6.2 dB and 0.4 dB, respectively. Next, we present the recent progress on optical CAM cell architectures, starting with an experimental demonstration of a 2-bit optical CAM match-line architecture that achieves an exact bitwise search operation of an incoming 2-bit destination address at 10 Gb s −1 , while the analysis is also extended to a numerical evaluation of a multi-cell 4-bit CAM-based row architecture with wavelength division multiplexed outputs for fast parallel memory operations at speeds of up to 4×20 Gb s −1 . Finally, we present a comparative study between electronic and optical RAMs and CAMs in terms of energy and speed and discuss the further challenges towards our vision. entries, even causing the depletion of the remaining IPv4 address space and leading to the advent of an IPv6 protocol with a quadrupled need for address look-up (AL) requirements [5]. This increasing need for faster routing functionalities, including AL, which also requires fast hardware memories to perform fast look-up of the packet's destination address immediately upon its arrival and across the forwarding information base (FIB) of the router.On the path to speeding up hardware memory and lower latency times when fetching data, state-of-the-art highly performing electronic static random access memory (RAM) cell technology has managed to achieve operation up to 5 GHz [6][7][8]. However, RAMs are inherently limited in fast AL as, owing to the address-based fetching of data, they would require multiple sequential random access to the memory and consecutive searches of the desired content. As a re...

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A 14 nm SoC platform technology featuring 2<sup>nd</sup> generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um<sup>2</sup> SRAM cells, optimized for low power, high performance and high density SoC products

Cited by 25 publications

References 0 publications

Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology

Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology

The Challenges of Advanced CMOS Process from 2D to 3D

Optical memory architectures for fast routing address look-up (AL) table operation

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