Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing

Gomes, Wilfred; Koker, Altug; Stover, Pat; Ingerly, D.; Siers, Scott; Venkataraman, Srikrishnan; Pelto, Chris; Shah, Tejas; Rao, Amreesh; O'Mahony, Frank; Karl, Eric; Cheney, Lance C; Rajwani, Iqbal; Jain, Hemant; Cortez, Ryan; Chandrasekhar, Arun G.; Kanthi, Basavaraj; Koduri, Raja

doi:10.1109/isscc42614.2022.9731673

Cited by 47 publications

(10 citation statements)

References 3 publications

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“…When it comes down to multi-core application, per-core individual power supply has been proven to be an energy saving system approach [48], [49]. Prior multiple-output designs mainly focused on how to effectively reuse a single power inductor for multiple outputs [50]- [52].…”

Section: F Multiple-output Hybrid Buckmentioning

confidence: 99%

“…For extremely compact 3D chiplet solution with advanced packaging technologies, we may have miniaturized package or parasitic inductors that only support sub-1A per inductor [66]- [68]. The IVR in [49] with an in-package substrate inductor called coaxial magnetic integrated inductor (CoaxMIL) [69] demonstrated ~86% peak efficiency for a 1.8V-to-0.7V conversion with over 1A per inductor.…”

Section: Design Considerationsmentioning

confidence: 99%

See 1 more Smart Citation

An Overview of Hybrid DC–DC Converters: From Seeds to Leaves

Lu,

Huang,

Tong

et al. 2024

IEEE Open J. Solid-State Circuits Soc.

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With the surging demands for higher current at sub-1V supply level in high performance digital systems, high-efficiency and high-current-density power converters are essential for system integration. Higher voltage supply buses are emerging for high current applications to reduce the IR losses on the power delivery networks. Thus, there is a wide voltage gap between the power bus and the digital supply rails at the point-of-load (PoL). Meanwhile, battery-powered portable or wearable devices favor extremely high-power-density solutions, calling for novel power conversion topologies, which has been the hottest topic in the power management IC area in the past decade. This paper reviews the switched-capacitor-inductor (SCI) hybrid DC-DC buck converters from the topology "seeds" to their "leaves". Here, we define six seeds, they are: 1) three-level buck, 2) double-step down buck, 3) inductor-first buck, 4) always-dual-path buck, 5) buck-buck, 6) multiple-output hybrid buck. We try to analyze and summarize their pros and cons, and to derive the evolution of the hybrid DC-DC converters, with milestone examples. Then, we share our observations, design intuitions and suggestions to help the researchers and engineers to pick up and design a new SCI hybrid DC-DC converter.

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Section: F Multiple-output Hybrid Buckmentioning

confidence: 99%

Section: Design Considerationsmentioning

confidence: 99%

An Overview of Hybrid DC–DC Converters: From Seeds to Leaves

Lu,

Huang,

Tong

et al. 2024

IEEE Open J. Solid-State Circuits Soc.

View full text Add to dashboard Cite

show abstract

“…However, traditional approaches have encountered bottlenecks due to the physical limits of processes, wafer yield restrictions, and thermal constraints imposed by packaging. As a result, more and more researchers have shifted their focus towards chiplet-based integration systems recently, exemplified by AMD's "zen2" processor [1], Intel's [2] Ponte Vecchio, and Tesla's DOJO [3].…”

Section: Introductionmentioning

confidence: 99%

DHRCA: A Design of Security Architecture Based on Dynamic Heterogeneous Redundant for System on Wafer

Mei,

Zhu,

et al. 2024

IET Information Security

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System on Wafer (SoW) based on chiplets may be implanted with hardware Trojans (HTs) by untrustworthy third-party chiplet vendors. However, traditional HTs protection techniques cannot guarantee complete protection against HTs, which poses a great challenge to the hardware security of SoW. In this paper, we propose a computing architecture based on endogenous security theory—dynamic heterogeneous redundant computing architecture (DHRCA) that can tolerate and detect HTs at runtime. The security of our approach is analyzed by building a generalized stochastic coloring petri net (GSCPN) model of DHRCA. The simulation results based on the GSCPN model show that our method can improve the system security probability to 0.8690 and the system availability probability to 0.9750 in the steady state compared with typical triple-mode redundancy and runtime monitoring methods. Furthermore, the impact of different attack and defense strategies on system security of different methods is simulated and analyzed in this paper.

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“…Third, it enables heterogeneous integration. Unlike logic circuits, analog circuit IPs do not significantly benefit from the performance and density improvements brought about by technological advancements [4], [16], [37], [53]. Therefore, manufacturing logic circuits with advanced technologies while producing various IO-functional analog IPs with more outdated processes can save on the expensive manufacturing and design and IPrelated costs associated with advanced technologies [4], [16], [36], [37].…”

Section: Background and Motivation A Trade-offs Introduced By Chipletmentioning

confidence: 99%

“…Unlike logic circuits, analog circuit IPs do not significantly benefit from the performance and density improvements brought about by technological advancements [4], [16], [37], [53]. Therefore, manufacturing logic circuits with advanced technologies while producing various IO-functional analog IPs with more outdated processes can save on the expensive manufacturing and design and IPrelated costs associated with advanced technologies [4], [16], [36], [37]. Fourth, the ability to repurpose a single chiplet for developing multiple computational chips, each differing in scale or targeted application, is a significant advantage of chiplet technology.…”

Section: Background and Motivation A Trade-offs Introduced By Chipletmentioning

confidence: 99%

Airframe Damage Region Division Method Based on Structure Tensor Dynamic Operator

Cai

Shi

2022

J. Shanghai Jiaotong Univ. (Sci.)

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Chiplet technology enables the integration of an increasing number of transistors on a single accelerator with higher yield in the post-Moore era, addressing the immense computational demands arising from rapid AI advancements. However, it also introduces more expensive packaging costs and costly Die-to-Die (D2D) interfaces, which require more area, consume higher power, and offer lower bandwidth than onchip interconnects. Maximizing the benefits and minimizing the drawbacks of chiplet technology is crucial for developing largescale DNN chiplet accelerators, which poses challenges to both architecture and mapping. Despite its importance in the post-Moore era, methods to address these challenges remain scarce.To bridge the gap, we first propose a layer-centric encoding method to encode Layer-Pipeline (LP) spatial mapping for largescale DNN inference accelerators and depict the optimization space of it. Based on it, we analyze the unexplored optimization opportunities within this space, which play a more crucial role in chiplet scenarios. Based on the encoding method and a highly configurable and universal hardware template, we propose an architecture and mapping co-exploration framework, Gemini, to explore the design and mapping space of large-scale DNN chiplet accelerators while taking monetary cost (MC), performance, and energy efficiency into account. Compared to the state-of-the-art (SOTA) Simba architecture with SOTA Tangram LP Mapping, Gemini's co-optimized architecture and mapping achieve, on average, 1.98× performance improvement and 1.41× energy efficiency improvement simultaneously across various DNNs and batch sizes, with only a 14.3% increase in monetary cost. Moreover, we leverage Gemini to uncover intriguing insights into the methods for utilizing chiplet technology in architecture design and mapping DNN workloads under chiplet scenarios. The Gemini framework is open-sourced at https://github.com/SET-Scheduling-Project/GEMINI-HPCA2024.

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Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing

Cited by 47 publications

References 3 publications

An Overview of Hybrid DC–DC Converters: From Seeds to Leaves

An Overview of Hybrid DC–DC Converters: From Seeds to Leaves

DHRCA: A Design of Security Architecture Based on Dynamic Heterogeneous Redundant for System on Wafer

Airframe Damage Region Division Method Based on Structure Tensor Dynamic Operator

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