M.P. Baze scite author profile

Results are presented of a study of SEU generated transient pulse attenuation in combinational logic structures built using common digital CMOS design practices. SPICE circuit analysis, heavy ion tests, and pulsed, focused laser simulations were used to examine the response characteristics of transient pulse behavior in long logic strings. Results show that while there is an observable effect, it cannot be generally assumed that attenuation will significantly reduce observed circuit bit error rates.

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A digital CMOS design technique for SEU hardening

Baze

Büchner

McMorrow

2000

IEEE Trans. Nucl. Sci.

105

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Single Event Upsets in Deep-Submicrometer Technologies Due to Charge Sharing

Amusan

Massengill

Baze

et al. 2008

IEEE Trans. Device Mater. Relib.

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Directional Sensitivity of Single Event Upsets in 90 nm CMOS Due to Charge Sharing

Amusan

Massengill

Baze

et al. 2007

IEEE Trans. Nucl. Sci.

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HBD layout isolation techniques for multiple node charge collection mitigation

Black

Sternberg

Alles

et al. 2005

IEEE Trans. Nucl. Sci.

105

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Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process

Amusan

Massengill

Baze

et al. 2008

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Single Event Upsets in a 130 nm Hardened Latch Design Due to Charge Sharing

Amusan

Steinberg

Witulski

et al. 2007

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M.P. Baze

Comparison of error rates in combinational and sequential logic

Attenuation of single event induced pulses in CMOS combinational logic

A digital CMOS design technique for SEU hardening

Single Event Upsets in Deep-Submicrometer Technologies Due to Charge Sharing

Directional Sensitivity of Single Event Upsets in 90 nm CMOS Due to Charge Sharing

HBD layout isolation techniques for multiple node charge collection mitigation

Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process

Single Event Upsets in a 130 nm Hardened Latch Design Due to Charge Sharing

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