Single Event Upsets in Deep-Submicrometer Technologies Due to Charge Sharing

Amusan, O.A.; Massengill, L.W.; Baze, M.P.; Sternberg, Andrew L.; Witulski, A.F.; Bhuva, B. L.; Black, Jeffrey D.

doi:10.1109/tdmr.2008.2000892

Cited by 93 publications

(29 citation statements)

References 13 publications

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“…For investigating single-event effects in ICs, the three-dimensional mixed-mode (TCAD) simulation has been confirmed to be a practical means [3,13,14,15]. Thus, with using the Sentaurus TCAD, the TCAD models in this paper are calibrated from commercial 65 nm bulk CMOS process design kit (PDK) to make sure that the electrical characteristics between them are matched well.…”

Section: Simulation Results and Analysismentioning

confidence: 99%

A radiation harden enhanced Quatro (RHEQ) SRAM cell

Peng

Chen

Zhang

et al. 2017

IEICE Electron. Express

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This paper intends to present a novel radiation-hardened SRAM cell by using the PMOS transistors stacked (each PMOS is split into two same sizes) and changing the inner topological structure on basis of the Quatro-10T. Combined with layout-level optimization design, the 3-D TCAD mixed-mode simulation results show that the novel design has a great single event upset (SEU) immune. Simultaneously, it is found to be tolerant of partial single-event multiple-node upsets (SEMNUs) due to the charge sharing among off-PMOS transistors. In addition, compared with the Quatro-10T, our proposed structure exhibits larger static noise margin (SNM) as well as lower power consumption in 65 nm COMS technology.

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Section: Simulation Results and Analysismentioning

confidence: 99%

A radiation harden enhanced Quatro (RHEQ) SRAM cell

Peng

Chen

Zhang

et al. 2017

IEICE Electron. Express

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“…more than critical charge for a single ion hit [8][9] (this is usually referred to as charge-sharing). The extent of MCU (the number of upset bits) represents the distance over which charge may diffuse and get collected by multiple SRAM cells.…”

Section: B32mentioning

confidence: 99%

Multi-cell soft errors at the 16-nm FinFET technology node

Tam

Bhuva

Massengill

et al. 2015

2015 IEEE International Reliability Physics Symposium

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“…The probability of such a failure depends on the location, magnitude, and duration of the transient glitch [17]. Charge sharing is a strong function of layout and distance between struck node and adjacent node [6]. In new cells, worst case happens when two nodes with the same potential (ST and N2 or STB and N1) are affected simultaneously.…”

Section: Multi-event Transient In New Cellsmentioning

confidence: 99%

“…1 shows an SRAM cell which is presented in our previous work [5]. In this SRAM cell for reducing charge sharing [6], same potential nodes (ST and N1 or STB and N2) are separated from each other [5]. Table 1 lists the sizes of transistors and threshold voltage level in reduced-charge-sharing SRAM cell (RCS-SRAM cell) presented in our previous work [5].…”

Section: Introductionmentioning

confidence: 99%