A radiation harden enhanced Quatro (RHEQ) SRAM cell

Peng, Chunyu; Chen, Ziyang; Zhang, Jingbo; Xiao, Songsong; Liu, Changyong; Wu, Xiulong; Lin, Zhiting

doi:10.1587/elex.14.20170784

Cited by 14 publications

(7 citation statements)

References 16 publications

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“…We also study the impact of the ion strike angles on the circuits. Angle 60°is widely used in simulations to evaluate the dependence of ion striking angle on SET [13,14,15]. So, in the angle striking simulations, the angle between the direction of ion striking and the +y-axis is set to 60°.…”

Section: P-hit 1)mentioning

confidence: 99%

An inverter chain with parallel output nodes for eliminating single-event transient pulse

Chang-yong

Lin

et al. 2019

IEICE Electron. Express

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The current paper presents an inverter chain with parallel output nodes design for the purpose of eliminating the single-event transient (SET) pulse. The structure of parallel output nodes combined with the layout utilizing isolation approach can eliminate the SET pulse substantially. As compared with the conventional inverter chain as well as the inverter chain of source-isolation approach and the duplicated inverter chains with C-element, the simulation results illustrate that the proposed inverter chain manifests an effective improvement of immunity to SET. With regard to P-hit, the proposed inverter chain is capable of attaining a stable output irrespective of the state of the struck PMOS being OFF or ON. With regard to N-hit, the proposed inverter chain can also maintain the final output steadily. As long as the SET pulse is not generated at the eventual output node, the pulse can be eliminated by the proposed inverter chain. Besides that, the proposed approach is also applicable to the circuits with the structure like inverter chain.

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Section: P-hit 1)mentioning

confidence: 99%

An inverter chain with parallel output nodes for eliminating single-event transient pulse

Chang-yong

Lin

et al. 2019

IEICE Electron. Express

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“…Three-dimensional mixed-mode TCAD simulation has been proven to be a useful means of investigating single-event effects (SEEs) in ICs [4,9,12,13,14,15,16,17,18,19]. In this work, we have adopted a Sentaurus TCAD from Synopsys, using 65 nm CMOS technology.…”

Section: Simulation Setupmentioning

confidence: 99%

A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination

Liu

Peng

Lin

et al. 2018

IEICE Electron. Express

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A dual-output design of inverter chain that is hardened against P-hit single-event transient (SET) is proposed in this paper. The output nodes of the proposed inverter chain are hardened by dual-output topological structure design and stacked PMOSs with isolation. The simulation results based on a 65 nm CMOS technology suggest that the proposed design can eliminate SET pulse significantly. In comparison with the conventional inverter chain and inverter chain using the source-isolation technique, the proposed design is capable of maintain the output steadily irrespective of whether an ion hits "0" or hits "1", i.e., the struck node is at logic "0" or logic "1". Besides, the SET pulse occurring at any stage of inverter chains with the proposed methodology will not disturb the final output, as long as it does not occur at the final stage.

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“…To mitigate SNUs or even DNUs, many designs of SRAM cells [4,[6][7][8][9][10][11][12][13][14][15] have been proposed by using the Radiation Hardening By Design (RHBD) approach. RHBD, which is also used for designing latches [16][17] and flip-flops [18][19][20], can effectively mitigate the impact of radiation particles on SRAM cells.…”

Section: Introductionmentioning

confidence: 99%

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors

Dou

Yan

Zhou

et al. 2020

2020 IEEE International Test Conference in Asia (ITC-Asia)

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In this paper, a highly reliable SRAM cell, namely SESRS cell, is proposed. Since the cell has a special feedback mechanism among its internal nodes and has more access transistors compared to a standard SRAM cell, the SESRS cell provides the following advantages: (1) it can self-recover from single node upsets (SNUs) and double-node upsets (DNUs); (2) it can reduce power consumption by 49.78% and silicon area by 7.92%, compared with the only existing SRAM cell which can self-recover from all possible DNUs. Simulation results validate the robustness of the proposed SESRS cell. Moreover, compared with the state-of-the-art hardened SRAM cells, the proposed SESRS cell can reduce read access time by 61.93% on average.

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A radiation harden enhanced Quatro (RHEQ) SRAM cell

Cited by 14 publications

References 16 publications

An inverter chain with parallel output nodes for eliminating single-event transient pulse

An inverter chain with parallel output nodes for eliminating single-event transient pulse

A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors

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