A digital CMOS design technique for SEU hardening

Baze, M.P.; Büchner, S.; McMorrow, D.

doi:10.1109/23.903815

Cited by 106 publications

(33 citation statements)

References 8 publications

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“…To improve soft error immunity, manufacturers of radiation-hardened ICs may use feedback elements (e.g., resistors, capacitors) to slow the propagation of voltage transients, at the expense of performance [5]. Other techniques to decrease soft error sensitivity include circuit design techniques that lead to increased transistor counts and layout area [6], [7]. While these techniques are quite effective, manufacturers of commercial ICs have been willing to implement them only on a very limited basis due to area and speed penalties [8], [9].…”

Section: Introductionmentioning

confidence: 99%

SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

Dodd

Shaneyfelt

Horn

et al. 2001

IEEE Trans. Nucl. Sci.

176

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Large-scale three-dimensional (3-D) device simulations, focused ion microscopy, and broadbeam heavy-ion experiments are used to determine and compare the SEU-sensitive volumes of bulk-Si and SOI CMOS SRAMs. Single-event upset maps and cross-section curves calculated directly from 3-D simulations show excellent agreement with broadbeam cross section curves and microbeam charge collection and upset images for 16 K bulk-Si SRAMs. Charge-collection and single-event upset (SEU) experiments on 64 K and 1 M SOI SRAMs indicate that drain strikes can cause single-event upsets in SOI ICs. 3-D simulations do not predict this result, which appears to be due to anomalous charge collection from the substrate through the buried oxide. This substrate charge-collection mechanism can considerably increase the SEU-sensitive volume of SOI SRAMs, and must be included in single-event models if they are to provide accurate predictions of SOI device response in radiation environments.

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Section: Introductionmentioning

confidence: 99%

SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

Dodd

Shaneyfelt

Horn

et al. 2001

IEEE Trans. Nucl. Sci.

176

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show abstract

“…Another transistor-level technique for soft-error mitigation is the dual-port design style proposed by Baze et al [9] and, later, by Zhang et al [132]. Dual-port gates, illustrated in Figure 1.13, decrease charge-collection efficiency, using two extra transistors placed in a separate well from the original transistors.…”

Section: Fault-tolerant Designmentioning

confidence: 99%

Design, Analysis and Test of Logic Circuits Under Uncertainty

Krishnaswamy¹,

Markov²,

Hayes³

2013

Lecture Notes in Electrical Engineering

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“…Some fault-tolerant storage circuits have been published previously [7] [8] [9] [10] [11]. The main drawback of these circuits is that they can only tolerate the SEUs inside the latch other than the sampled errors which originate in the preceding logic blocks.…”

Section: A Previous Published Hardened Storage Cellsmentioning

confidence: 99%

“…The main drawback of these circuits is that they can only tolerate the SEUs inside the latch other than the sampled errors which originate in the preceding logic blocks. Moreover, some architectures, [8] [9], are susceptible to particles with high energy [7], while others, [10] [11], cannot protect all the internal nodes of a latch [7]. Another approach called FERST, [7], can mitigate both SETs and SEUs, but can still be corrupted by timing errors.…”

Section: A Previous Published Hardened Storage Cellsmentioning

confidence: 99%

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SETTOFF: A fault tolerant flip-flop for building Cost-efficient Reliable Systems

Yang

Zwoliński

2012

2012 IEEE 18th International on-Line Testing Symposium (IOLTS)

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Abstract-Conventional fault tolerance techniques either require big overheads or have limited reliability. We propose a novel fault tolerant flip-flop (SETTOFF) that addresses timing errors and soft errors in one cost-efficient architecture. In SETTOFF, most SEUs are detected by monitoring the illegal transitions at the output of a flip-flop and recovered by inverting the cell state. SETs, timing errors and the other SEUs are detected by a time redundancy-based architecture. For a 10% activity rate, SETTOFF consumes 35.8% and 39.7% more power than a library flip-flop in 120nm and 65nm technologies, respectively. It only consumes about 5.7% more power than the detection based RazorII flip-flop [1]. The result indicates that SETTOFF is suitable for building high reliable systems at lower cost than the traditional techniques.

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A digital CMOS design technique for SEU hardening

Cited by 106 publications

References 8 publications

SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

Design, Analysis and Test of Logic Circuits Under Uncertainty

SETTOFF: A fault tolerant flip-flop for building Cost-efficient Reliable Systems

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