Design, Analysis and Test of Logic Circuits Under Uncertainty

Krishnaswamy, Smita; Markov, Igor L.; Hayes, John P.

doi:10.1007/978-90-481-9644-9

Cited by 9 publications

(6 citation statements)

References 128 publications

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“…Traditional methods for reliability improvement of logic circuits include using "hardened" cell libraries [17], [18], and fault masking [19], [20]. Our approach is different: it is based on adding a slow gate with a long inertial delay to the end of the path in order to stop propagation of short glitches representing SET; this is the effect of electrical attenuation [21]. In the experiment we use an example circuit described in Section II, where either the last stage only, or the last two stages are replaced with the gates of a different size.…”

Section: Stagementioning

confidence: 99%

Design-time reliability evaluation for digital circuits

Abufalgha

Bystrov

2017

2017 IEEE 23rd International Symposium on on-Line Testing and Robust System Design (IOLTS)

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A new method of evaluating the reliability of combinational circuits is proposed, this method uses two levels of characterisation: a Stochastic Fault Model (SFM) of the component library and a design-specific Critical Vector Model (CVM). The idea is to move the high-complexity problem of stochastic characterisation of parameters into the generic part of the design process, and do it just once for a great number of the specific designs. The SFM captures variations of the vector of parameters of a library component fault model, those causing a transient fault at the component output; it is meant to be supplied by the foundry, similar to timing library files. The CVM is derived by a limited number of simulation runs on the specific design, and represents the boundary between the erroneous and errorfree operation, w.r.t. the vector of parameters of each component. The probability of error-free operation is subsequently calculated by jointly using SFM and CVM. The method is demonstrated on a chain of inverters for simplicity, and subsequently applied to a 3-bit full adder. A complex three-way trade-off between energy, performance and reliability is explored. The method is meant to serve as a basis for design-time reliability evaluation and runtime power-reliability management. A slow stage is added to the circuit under test to improve its reliability.

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Section: Stagementioning

confidence: 99%

Design-time reliability evaluation for digital circuits

Abufalgha

Bystrov

2017

2017 IEEE 23rd International Symposium on on-Line Testing and Robust System Design (IOLTS)

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“…Gate level probabilistic models are designed based on the type of gates located in the circuit and the topological interconnections (serial or parallel, reconvergent fanouts) between the gates in the logic circuit [13]. Some of the probabilistic methods are Two Pass (TP) Algorithm, Signal Probability Algorithm (SPRA), Probabilistic Transfer Matrix (PTM) Algorithm etc.…”

Section: Gate Level Redundancymentioning

confidence: 99%

Analysis of Reliability for the Gate Level Fault Tolerant Design using Probabilistic Transfer Matrix method

Dixit¹

2017

IJCDS

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Abstract:As semiconductor integrated circuits entered into nanometer dimensions, large variations of parameters and drastic reduction in reliability conditions of the constituent devices may be expected. On basis of these unreliable concerns, the research in fault analysis and development of fault tolerant design methodologies are the growing concern nowadays. Design and development of the fault tolerant model of the system/circuit include two major areas. First, types of fault and the level of fault occurrence at the input and output of the circuit. Second, the analysis of reliability for the logic circuit. The aim of this paper is to improve the reliability and fault tolerance level of the logic circuit by introducing gate level redundancy with respect to the occurrence of transient fault. Triple Modular Redundancy methodology is used to design the fault tolerant model that improves the reliability of the logic circuit. The proposed Probability Transfer Matrix (PTM) algorithm evaluates and compares the reliability of the logic circuit without redundancy and with redundancy by the analytical formulations. The results of circuit reliability with respect to the gate error probability has been simulated for the occurrence of transient faults for the proposed logic circuits. The results have shown better improvement in reliability and fault tolerance level of 0.7% for the proposed logic circuit using gate level redundancy.

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“…Consequently, a transient noise pulse is generated due to the momentary current flowing through the device [4]. This single-event transient (SET), if propagated through subsequent circuitry and captured by a storage element, becomes a single-event upset (SEU), i.e., a bit error [1,5]. Such SEUs caused by the SETs are referred to as "soft" errors since there are no permanent damage to the hardware, and the rate at which they occur is called the soft error rate (SER).…”

Section: Introductionmentioning

confidence: 99%

“…With the advent of nanoscale computing, soft errors have become one of the most challenging issues that impact the reliability of modern electronic systems at ground level for the semiconductor industry [1,2]. A radiation-induced soft error occurs in a semiconductor device when the free mobile carriers generated by the passage of an energetic radiation particle are collected by the depletion region of a reverebiased p-n junction [3,4].…”

Section: Introductionmentioning

confidence: 99%

Accelerating soft-error-rate (SER) estimation in the presence of single event transients

Draper

2016

Proceedings of the 53rd Annual Design Automation Conference

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Radiation-induced soft errors have posed an ever increasing reliability challenge as device dimensions keep shrinking in advanced CMOS technology. Therefore, it is imperative to devise fast and accurate soft error rate (SER) estimation methods. Previous works mainly focus on improving the accuracy of the SER results, whereas the speed improvement is limited to partitioning and parallel processing. This paper presents an efficient SER estimation framework for combinational logic circuits in the presence of single-event transients (SETs). A novel top-down memoization algorithm is proposed to accelerate the propagation of SETs. Experimental results of a variety of benchmark circuits demonstrate that the proposed approach achieves up to 560.2X times speedup with less than 3% difference in terms of SER results compared with the baseline algorithm.

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Design, Analysis and Test of Logic Circuits Under Uncertainty

Cited by 9 publications

References 128 publications

Design-time reliability evaluation for digital circuits

Design-time reliability evaluation for digital circuits

Analysis of Reliability for the Gate Level Fault Tolerant Design using Probabilistic Transfer Matrix method

Accelerating soft-error-rate (SER) estimation in the presence of single event transients

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