Synchronizer circuits are usually characterized by their rate of failure in transmitting data between two independently timed regions. The mean time between failures

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Accurate measurement of edge time differences down to 10ps or less is required for tests of timing in digital systems. We describe a circuit aimed at reliably amplifying these time differences by a factor between 3 and 10 before measurement to enable greater accuracy.

The paper presents asynchronous design solutions to the problem of Priority Arbitration which is defined in the following form. A system consists of multiple, physically concurrent, processes with a shared resource. The discipline of resource allocation is a function of parameters of the active requests, which are assigned to the requests either statically or dynamically. This function can be defined in an (arbitrary) combinatorial way (contrary to conventional, 'topological', mappings, such as that used in a daisy-chain arbiter).The proposed designs are quasi-speed-independent. Furthermore, the priority logic, in the dynamic case, has the following architectural feature: it is a tree structure in which the control flow is maximally decoupled from the data-path by means of an early propagation of the 'valid'-'invalid' signals, concurrently with processing the priority data. This leads to significant reduction in the overall arbitration delay when the number of active requests is low.