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Processing-in-memory (PIM) chips that integrate processor logic into memory devices offer a new opportunity for bridging the growing gap between processor and memory speeds, especially for applications with high memory-bandwidth requirements. The Data-IntensiVe Architecture (DIVA) system combines PIM memories with one or more external host processors and a PIM-to-PIM interconnect. DIVA increases memory bandwidth through two mechanisms: (1) performing selected computation in memory, reducing the quantity of data transferred across the processor-memory interface; and (2) providing communication mechanisms called parcels for moving both data and computation throughout memory, further bypassing the processor-memory bus. DIVA uniquely supports acceleration of important irregular applications, including sparse-matrix and pointer-based computations. In this paper, we focus on several aspects of DIVA designed to effectively support such computations at very high performance levels: (1) the memory model and parcel definitions; (2) the PIM-to-PIM interconnect; and, (3) requirements for the processor-to-memory interface. We demonstrate the potential of PIMbased architectures in accelerating the performance of three irregular computations, sparse conjugate gradient, a natural-join database operation and an object-oriented database query.

Nonvolatile, flexible artificial synapses that can be used for brain-inspired computing are highly desirable for emerging applications such as human–machine interfaces, soft robotics, medical implants, and biological studies. Printed devices based on organic materials are very promising for these applications due to their sensitivity to ion injection, intrinsic printability, biocompatibility, and great potential for flexible/stretchable electronics. Herein, we report the experimental realization of a nonvolatile artificial synapse using organic polymers in a scalable fabrication process. The three-terminal electrochemical neuromorphic device successfully emulates the key features of biological synapses: long-term potentiation/depression, spike timing-dependent plasticity learning rule, paired-pulse facilitation, and ultralow energy consumption. The artificial synapse network exhibits an excellent endurance against bending tests and enables a direct emulation of logic gates, which shows the feasibility of using them in futuristic hierarchical neural networks. Based on our demonstration of 100 distinct, nonvolatile conductance states, we achieved a high accuracy in pattern recognition and face classification neural network simulations.

The DIVA (Data IntensiVe Architecture) system incorporates a collection of Processing-In-Memory (PIM) chips as smart-memory co-processors to a conventional microprocessor. We have recently fabricated prototype DIVA PIMs. These chips represent the first smart-memory devices designed to support virtual addressing and capable of executing multiple threads of control. In this paper, we describe the prototype PIM architecture. We emphasize three unique features of DIVA PIMs, namely, the memory interface to the host processor, the 256-bit wide datapaths for exploiting on-chip bandwidth, and the address translation unit. We present detailed simulation results on eight benchmark applications. When just a single PIM chip is used, we achieve an average speedup of 3.3X over host-only execution, due to lower memory stall times and increased fine-grain parallelism. These 1-PIM results suggest that a PIM-based architecture with many such chips yields significantly higher performance than a multiprocessor of a similar scale and at a much reduced hardware cost.

Abstract-Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upsetting the logic state of memory circuits. In this paper we investigate the critical charge (Q crit ) required to upset a 6T SRAM cell designed in a commercial 90nm process. We characterize Q crit using different current models and show that there are significant differences in Q crit values depending on which models are used. Discrepancies in critical charge characterization are shown to result in under-predictions of the SRAM's associated soft error rate as large as two orders of magnitude. For accurate Q crit calculation, it is critical that 3D device simulation is used to calibrate the current pulse modeling heavy ion strikes on the circuit, since the stimuli characteristics are technology feature size dependant. Current models with very fast characteristic timing parameters are shown to result in conservative soft error rate predictions; and can assertively be used to model ion strikes when 3D simulation data is not available.