Accelerating soft-error-rate (SER) estimation in the presence of single event transients

Abstract

Radiation-induced soft errors have posed an ever increasing reliability challenge as device dimensions keep shrinking in advanced CMOS technology. Therefore, it is imperative to devise fast and accurate soft error rate (SER) estimation methods. Previous works mainly focus on improving the accuracy of the SER results, whereas the speed improvement is limited to partitioning and parallel processing. This paper presents an efficient SER estimation framework for combinational logic circuits in the presence of single-event transients (SETs). A novel top-down memoization algorithm is proposed to accelerate the propagation of SETs. Experimental results of a variety of benchmark circuits demonstrate that the proposed approach achieves up to 560.2X times speedup with less than 3% difference in terms of SER results compared with the baseline algorithm.

Yield modelling and analysis of bundled data and ring‐oscillator based designs

“…The "on" state time t on is calculated by multiplying the total circuit operation time t op by the probability of "on" state p on (i.e., V gs = 0) of the PMOS, i.e., t on = t op • p on . According to [20], the probability of logic "on" state can be calculated using two approaches: (i) the correlation coefficient method (CCM) approach proposed in [21], or (ii) simulations over a large set of typical vectors (possibly obtained by running a set of benchmark programs). In this paper, the first approach is adopted.…”

“…. According to [21], the probability of logic ‘on’ state can be calculated using two approaches: (i) the correlation coefficient method approach proposed in [22], or (ii) simulations over a large set of typical vectors (possibly obtained by running a set of benchmark programs). In this paper, the first approach is adopted.…”

Modeling and Simulation of Low Power Single Event Upset-resilient SRAM cell

“…Data corruption and system failures because of the inability to eliminate radiation induced soft errors might have dangerous results in mission critical systems such as mainstream servers, automobile, and spacecrafts [10][11]. With technology scaling reaching deep submicron dimensions of less than 250nm, frequency of operation reaching to 100MHz and the increased speed and complexity of around a million gates in a circuit, Single Event Transient (SET) issues became a commonly occurring problem by the end of the 90s [12]. Therefore, SET tolerance needs to be a part of all logic circuits, especially in critical applications [13].…”

Hardware-driven nonlinear activation for stochastic computing based deep convolutional neural networks

“…Stochastic Computing (SC), which uses the probability of 1s in a random bit stream to represent a number, has the potential to enable massively parallel and ultra-low footprint hardware based DCNNs [10,[14][15][16][17]. In SC, arithmetic operations like multiplication can be performed using simple logic elements and SC provides better soft error resiliency [15,[18][19][20]. In this regard, considerable efforts have been invested in the context of designing Artificial Neural Networks (ANNs), Deep Belief Network (DBNs) and DCNNs using SC components [10,14,16,17,[21][22][23].…”