Directional Sensitivity of Single Event Upsets in 90 nm CMOS Due to Charge Sharing

Amusan, O.A.; Massengill, L.W.; Baze, M.P.; Bhuva, B. L.; Witulski, A.F.; DasGupta, Sandeepan; Sternberg, Andrew L.; Fleming, P.R.; Heath, Christopher C.; Alles, Michael L.

doi:10.1109/tns.2007.907989

Cited by 82 publications

(23 citation statements)

References 9 publications

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“…The total area of one Double-DICE latch is compared to the area of two DICE latches with the sensitive node separations of 8.5 µm and 5µm (minimum suggested distance between sensitive nodes [8]) in Table 1. Table 1 shows that the Double-DICE latch has 33.33 % less area compared to a pair of DICE latches with a sensitive nodal distance of 8.5 µm; the area saving drops to 8 % when a sensitive nodal separation of 5 µm is used.…”

Section: Implementation and Resultsmentioning

confidence: 99%

“…Recent studies have shown that bipolar amplification between PMOS devices due to the n-well potential collapse and charge diffusion between NMOS devices in the case of a single strike are the main charge sharing mechanisms [7]. Through 3-D Technology ComputerAided Design (TCAD) simulations, Amusan et al, showed that the n-well potential collapse from an angular strike with a Linear Energy Transfer (LET) of 21 MeV.cm 2 /mg can extend as far as 5 µm from the strike location for a 90 nm technology [8]. Therefore, any hardened design with sensitive PMOS pairs located within this distance are susceptible to parasitic bipolar effects.…”

Section: Introductionmentioning

confidence: 99%

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The 90 nm Double-DICE storage element to reduce Single-Event upsets

Haghi

Draper

2009

2009 52nd IEEE International Midwest Symposium on Circuits and Systems

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-In this paper, we introduce the Double-DICE storage element, which reduces charge sharing and collecting between the sensitive nodes of sensitive pairs in a Dual Interlocked Cell (DICE) storage cell in 90 nm technology. Interleaving two DICE storage cells in layout separates sensitive nodes by 8.5 µm, which is well beyond the minimum required of 5 µm shown in an earlier work. This reduces the probability of charge collecting in a sensitive pair in one DICE caused by a Single-Event strike. An area savings of 33.3 % results as compared to the case where no interleaving is used with the same nodal separation.

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Section: Implementation and Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

The 90 nm Double-DICE storage element to reduce Single-Event upsets

Haghi

Draper

2009

2009 52nd IEEE International Midwest Symposium on Circuits and Systems

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“…In common CMOS process, the radiation hardened by design (RHBD) layout methods have been proposed to enhance the SET tolerance [1,2,3,4,5,6,7]. Charge sharing techniques and SETs model are used to mitigate SET effects [8,9].…”

Section: Introductionmentioning

confidence: 99%

A single-event transient hardened LDO regulator with built-in filter

Zhang

Ding

Liu

et al. 2015

IEICE Electron. Express

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A single-event transient (SET) hardened LDO using novel structure is proposed to enhance the single-event effect tolerance. The novel LDO with built-in filter can mitigate the response of the sensitive nodes of circuit. If the SET pulse current flows through the sensitive nodes, the maximum variation of the output voltage is only 15.5 mV. In addition, the transient performance is slightly dropped back as a tradeoff for the built-in filter. When the workload changes transiently between 100 µA and 100 mA in 100 ns, the undershoot is 28.4 mV and the overshoot is nearly 20 mV with imperceptible peak.

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“…After several decades, the mechanisms of SET have already been explored in common bulk CMOS technologies and the charge collection is controlled by drift, diffusion and bipolar effect [2,3,4]. The previous investigations indicated that the bipolar effect is the main mechanism in PMOSFET [5]. The research also showed that most of the SET comes from the ion striking PMOSFETs but not NMOSFETs due to the significant bipolar effect [6,7].…”

Section: Introductionmentioning

confidence: 99%

“…So SET mitigation in PMOSFET becomes a more important issue. In order to reduce the threat of SET in IC in bulk CMOS process, several efficient radiation hardened by design (RHBD) layout techniques are proposed for SET mitigation [5,7,8,9,10,11]. However, none of these RHBD techniques can significantly reduce SET pulse width.…”

Section: Introductionmentioning

confidence: 99%

Research on single-event transient mechanism in a novel SOI CMOS technology

Zhang

Chen

Chi

et al. 2014

IEICE Electron. Express

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For the first time, compared with common bulk PMOSFETs, single-event transient (SET) mechanism was researched in a novel SOI PMOSFETs using technology computer-aided design mixed-mode numerical (TCAD) simulations. The simulation results showed that, different from the common bulk CMOS technology, diffusion but not bipolar effect is the main mechanism in PMOSFETs fabricated in this novel SOI CMOS technology. The effects of buried oxide (BOX) layer and body tie on SET were also discussed for the PMOSFETs in this technology. The radiation hardened by design (RHBD) layout technique was proposed for further SET mitigation. All of the studies indicated that this novel SOI CMOS technology has the essential advantage for radiation hardened integrated circuit (IC) design.

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Directional Sensitivity of Single Event Upsets in 90 nm CMOS Due to Charge Sharing

Cited by 82 publications

References 9 publications

The 90 nm Double-DICE storage element to reduce Single-Event upsets

The 90 nm Double-DICE storage element to reduce Single-Event upsets

A single-event transient hardened LDO regulator with built-in filter

Research on single-event transient mechanism in a novel SOI CMOS technology

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