In this paper, a novel layout technique for N-hit single-event transient (SET) mitigation that is based on source-extension is proposed. Based on 65 nm bulk CMOS technology, both mixed-mode numerical simulations with technology computer-aided design (TCAD), as well as heavy-ion experiments show SET pulse widths are efficiently reduced with source extension.As opposed to what is found in the P-hit SET production process, where the source plays a detrimental role in SET mitigation due to the well-known bipolar effect, in the N-hit SET production process the source plays a beneficial role in reducing SET pulse widths, attributable to a parasitic reversed bipolar effect. This effect will be discussed in depth in this paper, and the proposed 'radiation hardened by design' (RHBD) layout technique will be extended to common combinational standard cells. The area penalty will also be discussed for the proposed layout technique. Meanwhile, both the P-hit and N-hit SET mitigation layout techniques will be introduced into the standard inverter layout, and the final improvement in SET pulse width will be discussed. Index Terms-Novel layout technique via source-extension, parasitic reversed bipolar effect, radiation hardened by design (RHBD), single-event transient (SET).

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Plasma-enhanced chemical vapor deposition (PECVD) is widely used for the synthesis of carbon materials, such as diamond-like carbons (DLCs), carbon nanotubes (CNTs) and carbon nanowalls (CNWs). Advantages of PECVD are low synthesis temperature compared with thermal CVD and the ability to grow vertically, free-standing structures. Due to its self-supported property and high specific surface area, CNWs are a promising material for field emission devices and other chemical applications. This article reviews the recent process on the synthesis of CNW by the PECVD method. We briefly introduce the structure and properties of CNW with characterization techniques. Growth mechanism is also discussed to analyze the influence of plasma conditions, substrates, temperature, and other parameters to the final film, which will give a suggestion on parameter modulation for desired film.

Based on three-dimensional (3D) technology computer aided design (TCAD) simulations, the supply voltage and temperature dependence of single-event transient (SET) pulse width in 28-nm fully-depleted silicon-on-insulator (FDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated. FDSOI MOSFETs are symmetry devices with a superior control of the short channel effects (SCEs) and single-event effects (SEEs). Previous studies have suggested that the SET width is invariant when the temperature changes in FDSOI devices. Simulation results show that the SET pulse width increases as the supply voltage decreases. When the supply voltage is below 0.6 V, the SET pulse width increases sharply with the decrease of the supply voltage. The SET pulse width is not sensitive to temperature when the supply voltage is 1 V. However, when the supply voltage is 0.6 V or less, the SET pulse width exhibits an anti-temperature effect, and the anti-temperature effect is significantly enhanced as the supply voltage drops. Besides, the mechanism is analyzed from the aspects of saturation current and charge collection.

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