Heavy-Ion-Induced Charge Sharing Measurement With a Novel Uniform Vertical Inverter Chains (UniVIC) SEMT Test Structure

Huang, Pengcheng; Chen, Shuming; Chen, Jianjun; Liang, Bin; Chi, Yaqing

doi:10.1109/tns.2015.2486774

Cited by 33 publications

(16 citation statements)

References 20 publications

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“…SET generates in the target circuit (TC). TC is the same in structure as the target circuit of Reference [8]. The 800-level inverter chain is divided into 4200-level short chains and connected to the measurement circuit through the OR4 gate.…”

Section: Test Chip Structurementioning

confidence: 99%

“…As process feature sizes continue to shrink, clock frequencies continue to increase, node capacitance and supply voltage decrease, the critical charge of transient pulses is reduced [3][4][5], and waveforms are more easily captured and soft errors are formed. It has been reported that SET are the main cause of soft errors in space applications [6,7], and charge sharing may even affect multiple nodes and cause single-event multiple transients (SEMT) [8][9][10]. These problems are already common in combinatorial logic circuits.…”

Section: Introductionmentioning

confidence: 99%

“…In other processes, there are also examples [3,9,13,14] of successful use of this measurement method. On the basis of this method, Huang et al [8] proposed a structure that can simultaneously measure multiple transient pulses, using eight capture circuits to share a self-trigger structure design, which can measure the SEMT. This improvement has also been widely used by researchers [6,10,18].…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, the heavy-ion induced SET pulse measurement structure proposed in Reference [8] is used and some additional measures are taken. A test chip was fabricated in a 28 nm bulk silicon process using eight inverter chains as a sensitive target circuit.…”

Section: Introductionmentioning

confidence: 99%

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Investigation of Heavy-Ion Induced Single-Event Transient in 28 nm Bulk Inverter Chain

Liang

Chi

et al. 2020

Symmetry

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The reliability of integrated circuits under advanced process nodes is facing more severe challenges. Single-event transients (SET) are an important cause of soft errors in space applications. The SET caused by heavy ions in the 28 nm bulk silicon inverter chains was studied. A test chip with good symmetry layout design was fabricated based on the 28 nm process, and the chip was struck by using 5 kinds of heavy ions with different linear energy transfer (LET) values on heavy-ion accelerator. The research results show that in advanced technology, smaller sensitive volume makes SET cross-section measured at 28 nm smaller than 65 nm by an order of magnitude, the lower critical charge required to generate SET will increase the reliability threat of low-energy ions to the circuit, and high-energy ions are more likely to cause single-event multiple transient (SEMT), which cannot be ignored in practical circuits. The transients pulse width data can be used as a reference for SET modeling in complex circuits.

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Section: Test Chip Structurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Investigation of Heavy-Ion Induced Single-Event Transient in 28 nm Bulk Inverter Chain

Liang

Chi

et al. 2020

Symmetry

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“…As shown in Figure 7( in twin-well structure, with ion striking at L1 with LET of 25 MeV · cm 2 · mg −1 , charge sharing between P0 and P1 is strong, and then the SET in D and CLK is large enough to cause an upset in DFF. However, in triple-well structure, the deep N+ well (DNW) layer [6,[19][20][21] can mitigate PBE effectively, so that charge sharing in n-well is mitigated greatly as well. As shown in Figure 7(b), for the same ion strike location, even the LET is 55 MeV · cm 2 · mg −1 , the amplitude of the SET in CLK is not over 0.5 V, and then no SEU occurs.…”

Section: The Well-structure Dependency Of Sedt-induced Seumentioning

confidence: 99%

Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology

Huang

Chen

2016

Sci. China Inf. Sci.

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Single event upset (SEU) is one of the most important origins of soft errors in aerospace applications. As technology scales down persistently, charge sharing is playing a more and more significant effect on SEU of flip-flop. Charge sharing can often bring about multi-node charge collection in storage nodes and non-storage nodes in a flip-flop. In this paper, multi-node charge collection in flip-flop data input and flip-flop clock signal is investigated by 3D TCAD mixed-mode simulations, and the simulate results indicate that single event double transient (SEDT) in flip-flop data input and flip-flop clock signal can also cause a SEU in flip-flop. This novel mechanism is called the SEDT-induced SEU, and it is also verified by heavy-ion experiment in 65 nm twin-well process. The simulation results also indicate that this mechanism is closely related with the well-structure, and the triple-well structure is more effective to increase the SEU threshold of this mechanism than twin-well structure.Keywords single event upset (SEU), single event double transient (SEDT), SEDT-induced SEU, parasitic bipolar effect (PBE), charge sharing CitationHuang P C, Chen S M, Chen J J. Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology. Sci China Inf Sci,

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Comparison of D-flip-flops and D-latches: influence on SET susceptibility of the clock distribution network

Hao

Chen

2019

NUCL SCI TECH

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Heavy-Ion-Induced Charge Sharing Measurement With a Novel Uniform Vertical Inverter Chains (UniVIC) SEMT Test Structure

Cited by 33 publications

References 20 publications

Investigation of Heavy-Ion Induced Single-Event Transient in 28 nm Bulk Inverter Chain

Investigation of Heavy-Ion Induced Single-Event Transient in 28 nm Bulk Inverter Chain

Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology

Comparison of D-flip-flops and D-latches: influence on SET susceptibility of the clock distribution network

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