Impact of Circuit Placement on Single Event Transients in 65 nm Bulk CMOS Technology

He, Yuhui; Chen, Shuming; Chen, Jianjun; Chi, Yaqing; Liang, Bin; Liu, Biwei; Qin, Jun-Rui; Du, Yi; Huang, Pengcheng

doi:10.1109/tns.2012.2218256

Cited by 34 publications

(8 citation statements)

References 19 publications

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“…6(a The unhardened commercial standard cell's pulse-width, which is analyzed in Ref. [1], focus on 40 to 440 ps for the VP inverter chain using Krypton with LET of 40.5 MeV cm 2 /mg. Fig.…”

Section: Experimental and Resultsmentioning

confidence: 99%

Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

Li¹,

Wu²,

Yang³

et al. 2017

J. Semicond.

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With the critical charge reduced to generate a single event effect (SEE) and high working frequency for a nanometer integrated circuit, the single event effect (SET) becomes increasingly serious for high performance SOC and DSP chips. To analyze the radiation-hardened method of SET for the nanometer integrated circuit, the n+ guard ring and p+ guard ring have been adopted in the layout for a 65 nm commercial radiation-hardened standard cell library. The weakest driving capacity inverter cell was used to evaluate the single event transient (SET) pulse-width distribution. We employed a dual-lane measurement circuit to get more accurate SET’s pulse-width. Six kinds of ions, which provide LETs of 12.5, 22.5, 32.5, 42, 63, and , respectively, have been utilized to irradiate the SET test circuit in the Beijing Tandem Accelerator Nuclear Physics National Laboratory. The testing results reveal that the pulse-width of most SETs is shorter than 400 ps in the range of LETeff from to and the pulse-width presents saturation tendency when the effective linear energy transfer (LETeff) value is larger than . The test results also show that the hardened commercial standard cell’s pulse-width concentrates on 33 to 264 ps, which decreases by 40% compared to the pulse-width of the 65 nm commercial unhardened standard cell.

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“…6(a The unhardened commercial standard cell's pulse-width, which is analyzed in Ref. [1], focus on 40 to 440 ps for the VP inverter chain using Krypton with LET of 40.5 MeV cm 2 /mg. Fig.…”

Section: Experimental and Resultsmentioning

confidence: 99%

Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

Li¹,

Wu²,

Yang³

et al. 2017

J. Semicond.

View full text Add to dashboard Cite

show abstract

“…To match the current drive, the width of the PMOS transistor is about several times larger than the width of the NMOS transistor. It results in a large sensitive drain region for PMOS transistors [21,22,23]. Moreover, the bipolar amplification effect also significantly influences the PMOS transistors at high LET [24].…”

Section: P-hit and N-hit Set Cross Sectionsmentioning

confidence: 99%

Characterization of P-hit and N-hit single-event transient using heavy ion microbeam

Song

Shao

Liang

et al. 2019

IEICE Electron. Express

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P-hit and N-hit single-event transients are investigated using heavy ion microbeam. A novel layout placement was implemented in the test chip to distinguish SETs originating from P-hit and N-hit. Experimental results indicate both the P-hit and N-hit SETs show an exponentiallike distribution in all target circuits. The SET cross sections and the average pulse width for P-hit and N-hit are also investigated. The well process, the transistor size and the layout topology significantly impact on the cross sections. Only the transistor size impacts on the average pulse width at low LET.

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“…It was previously shown that vertical placement, i.e. electrically connected cells placed in different cell rows, eliminates the pulse quenching effect due to the increased nodal separation and the presence of the well contacts which considerably reduces the charge sharing efficiency [17]. To calculate the SET crosssection a script routine is used to automate the fault injection and to measure the transient pulses.…”

Section: Electrical Simulationmentioning

confidence: 99%

Analysis of the charge sharing effect in the SET sensitivity of bulk 45 nm standard cell layouts under heavy ions

Aguiar

Wrobel

Autran

et al. 2018

Microelectronics Reliability

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For nanometer technologies, SET is increasingly growing in importance in circuit design. Accordingly, different hardening techniques were developed to reduce the Soft-Error Rate. Considering selective node hardening technique based on standard cells, this work evaluates the SET response of logic gates from a Standard-Cell library under heavy ions. Overall, it is observed that the usage of NOR and NAND gates coupled with an output inverter provides reduced SET cross-section and increased threshold LET compared with the standalone OR gate and AND gate, respectively. With the results gathered in this work, circuit designers can implement reliability-aware synthesis algorithms with selective hardening more efficiently to tackle the threat of SET in combinational circuits.

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Impact of Circuit Placement on Single Event Transients in 65 nm Bulk CMOS Technology

Cited by 34 publications

References 19 publications

Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

Characterization of P-hit and N-hit single-event transient using heavy ion microbeam

Analysis of the charge sharing effect in the SET sensitivity of bulk 45 nm standard cell layouts under heavy ions

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Impact of Circuit Placement on Single Event Transients in 65 nm Bulk CMOS Technology

Cited by 34 publications

References 19 publications

Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

Characterization of P-hit and N-hit single-event transient using heavy ion microbeam

Analysis of the charge sharing effect in the SET sensitivity of bulk 45 nm standard cell layouts under heavy ions

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Product

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Analysis of the charge sharing effect in the SET sensitivity of bulk 45 nm standard cell layouts under heavy ions