Single Event Upsets in a 130 nm Hardened Latch Design Due to Charge Sharing

Amusan, O.A.; Steinberg, A.L.; Witulski, A.F.; Bhuva, B. L.; Black, Jeffrey D.; Baze, M.P.; Massengill, L.W.

doi:10.1109/relphy.2007.369908

Cited by 53 publications

(19 citation statements)

References 13 publications

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“…With technology scaling down, the charge sharing between neighboring SRAM cells is strengthened to cause multi single event upsets (SEUs), and increase the radiation immunity of SRAMs in many studies [2,3]. Moreover, many previous conclusions about the sensitivity of SRAMs are no longer applicable for advanced technologies because of charge sharing.…”

Section: Introductionmentioning

confidence: 99%

Effect of charge sharing on SEU sensitive area of 40-nm 6T SRAM cells

Zhang

et al. 2014

IEICE Electron. Express

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Abstract:The effect of charge sharing on single event upset (SEU) sensitive area of SRAM cells is studied in a 40-nm bulk CMOS technology. All transistors in a 6T SRAM cell are simulated in 3D TCAD models, and SEU sensitive areas are measured in different simulation conditions. We find the charge sharing can reduce SEU sensitive area of SRAM cells. The effect of charge sharing on radiation sensitivity of both PMOS and NMOS are analyzed in depth. The works in this paper can guide the single event rate prediction and the hardened design of SRAMs in advanced technologies.

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Section: Introductionmentioning

confidence: 99%

Effect of charge sharing on SEU sensitive area of 40-nm 6T SRAM cells

Zhang

et al. 2014

IEICE Electron. Express

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“…This can be achieved by simply adding inverters at the input and output pins. Additional hardening can be applied by spatially separating the storage nodes to decrease the probability of multiple node charge collection from a single ion strike, which has been shown to cause upsets even at low LET [26].…”

Section: ) Dual Interlock Storage Cellsmentioning

confidence: 99%

Redundancy Based on a Fault-Tolerant Gate Array Cell

Tyurin¹,

Kamenskih²

2017

VVSUTR

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Radiation hardening by design (RHBD) has become a necessary practice when creating circuits to operate within radiated environments. While employing RHBD techniques has tradeoffs between size, speed and power, novel designs help to minimize these penalties. Space radiation is the primary source of radiation errors in circuits and two types of single event effects, single event upsets (SEU), and single event transients (SET) are increasingly becoming a concern. While numerous methods currently exist to nullify SEUs and SETs,

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“…Triple mode redundancy (TMR) on advanced nodes has demonstrated the need to provide spatial separation of redundant circuits to avoid their coincident upset, i.e., domain crossing errors [29]. MNCC due to one impinging particle generating charge has also made hardened FF design more difficult, requiring careful physical design as well as clever circuits [27][28] [30].…”

Section: Radiation Hardening By Designmentioning

confidence: 99%

An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits

Clark

Patterson

Ramamurthy

et al. 2016

IEEE Trans. Comput.

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A radiation hardened by design embedded microprocessor is presented. The design uses multiple approaches to minimize the performance reduction from hardening, while simultaneously limiting the power increase. The speculative portions of the pipeline are protected by microarchitecture approaches, i.e., the speculative pipeline is dual redundant, whereby instructions that have errors in one copy cause a pipeline restart-only matching results commit to architectural state. The register file is dual redundant with mechanisms for correction using one copy whose parity is correct. The data cache memory is write-through, allowing protection with parity. The remaining architectural state is protected via hardened circuits. These are implemented with self-correcting triple mode redundant (TMR) flip-flops and TMR logic. The design, implemented here on a 90-nm bulk CMOS process, achieves unprecedented single event effects hardness and 400+ MHz operating frequency at less than 500 mW power consumption. The main constituent circuit hardening approaches have been fabricated and tested separately. Broad beam testing of the constituent circuits has resulted in no uncorrectable soft errors below 100 MeV-cm 2 /mg LET EFF . We describe the CAD flows used to ensure node separation to achieve high immunity to multiple node charge collection and discuss the relative costs of the chosen hardening techniques.Index Terms-Radiation hardening by design (RHBD); microprocessor; cache memory; total ionizing dose; single event transients, soft error mitigation, single-event effects.

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Single Event Upsets in a 130 nm Hardened Latch Design Due to Charge Sharing

Cited by 53 publications

References 13 publications

Effect of charge sharing on SEU sensitive area of 40-nm 6T SRAM cells

Effect of charge sharing on SEU sensitive area of 40-nm 6T SRAM cells

Redundancy Based on a Fault-Tolerant Gate Array Cell

An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits

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