Attenuation of single event induced pulses in CMOS combinational logic

Abstract

Results are presented of a study of SEU generated transient pulse attenuation in combinational logic structures built using common digital CMOS design practices. SPICE circuit analysis, heavy ion tests, and pulsed, focused laser simulations were used to examine the response characteristics of transient pulse behavior in long logic strings. Results show that while there is an observable effect, it cannot be generally assumed that attenuation will significantly reduce observed circuit bit error rates.

MARS-C: modeling and reduction of soft errors in combinational circuits

“…One obvious approach is to inject the fault into the given node of the circuit and simulate the circuit for different input vectors in order to find whether the fault propagates [11][12]. However, this approach becomes intractable for larger circuits and larger number of inputs.…”

“…Intensive research has been done so far in the area of analysis and modeling the effect of transient faults in logic circuits [5][6][7][8][9][10][11][12]. One obvious approach is to inject the fault into the given node of the circuit and simulate the circuit for different input vectors in order to find whether the fault propagates [11][12].…”

Circuit Reliability Analysis Using Symbolic Techniques

“…In addition, the time when the glitch becomes less than V S,latch (t 2 ') must satisfy: (6) with duration D of the glitch at output F given by equation (3). Thus, we can write the condition which allows a glitch occurring at gate G to be latched, as: ) , (…”

“…However, for estimating the likelihood of soft errors as the result of a SEU, most of the previous work has relied on fault injection [1,6,7] and simulation instead of the symbolic modeling of the probability of soft errors. The results presented by Mohanram et al [1] show that soft error susceptibility of internal nodes in a logic circuit can vary by at least one order of magnitude.…”

A highly-efficient technique for reducing soft errors in static CMOS circuits

“…But, it masks SEU errors only in CLBs and has higher overhead compared to the technique presented in this work [8]. Prior efforts have also focused on latch design for mitigating soft errors [9], [10] and combinational logic design for preventing pulse spreading [11]. Our technique uses a delay line that is common to one or more combinational logic blocks (CLBs) as opposed to a delay line within each latch as done in [10].…”