Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process

Amusan, O.A.; Massengill, L.W.; Baze, M.P.; Bhuva, B. L.; Witulski, A.F.; Black, Jeffrey D.; Balasubramanian, A.; Casey, Megan C.; Black, Dolores A.; Ahlbin, J. R.; Reed, Robert A.; McCurdy, Michael W.

doi:10.1109/relphy.2008.4558930

Cited by 27 publications

(20 citation statements)

References 10 publications

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“…Previous works have shown that charge collection for P-hits is dominated by bipolar amplification, while it is dominated by drift and diffusion for N-hits [18], [19]. Therefore, the SET pulse will not be affected by the body-biasing voltage for N-hits.…”

Section: Dependency Of Charge Collection On Body Bias For N-hitmentioning

confidence: 99%

Simulation Study of the Single-Event Effects Sensitivity in Nanoscale CMOS for Body-Biasing Circuits

Qin

Chen

Guo

et al. 2014

IEEE Trans. Device Mater. Relib.

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The sensitivity of single-event effects (SEEs) in nanoscale CMOS for body-biasing circuits has been investigated. For PMOS hits, it is found that forward-biasing the body for high-speed applications can suppress the SET pulses greatly. Reverse-biasing the body for low-power applications, however, does not reduce the SEE vulnerability compared with operation when the body grounded. The body-biasing voltage has no impact on SEE sensitivity for NMOS hits.Index Terms-Body-biasing, single-event effects (SEEs), charge sharing effect, pulse quenching.

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Section: Dependency Of Charge Collection On Body Bias For N-hitmentioning

confidence: 99%

Simulation Study of the Single-Event Effects Sensitivity in Nanoscale CMOS for Body-Biasing Circuits

Qin

Chen

Guo

et al. 2014

IEEE Trans. Device Mater. Relib.

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“…For smaller transistors, statistically less number of electron-hole pairs are expected to be generated for same number of radiation strikes (the average interaction length is longer for bigger transistors, since the radiation strikes are not always vertical) [6]. As a result, smaller amount of charge will be generated for a radiation strike in case of VCO-DBR as compared to VCO-SBR, improving SET tolerance.…”

Section: Reduced Set Charge Generationmentioning

confidence: 99%

Design of SET tolerant LC oscillators using distributed bias circuitry

Jagtap

Sharma

Gupta

2015

Microelectronics Reliability

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“…Since quenching is closely related to multi-node charge collection, understanding the mechanism of multi-node charge collection will facilitate the analysis of quenching effect. Previous works [11,12] have studied the relationship between charge collected by active/passive device and layout spacing and LET in 130 and 90 nm CMOS technologies. By analyzing all the above, the propagation delay of electrical signal, layout spacing and the energy of striking particles have critical effects on quenching, but there is no relevant research so far.…”

Section: Related Workmentioning

confidence: 99%

Research on single event transient pulse quenching effect in 90 nm CMOS technology

Qin

Chen

Liu

et al. 2011

Sci. China Technol. Sci.

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Since single event transient pulse quenching can reduce the SET (single event transient) pulsewidths effectively, the charge collected by passive device should be maximized in order to minimize the propagated SET. From the perspective of the layout and circuit design, the SET pulsewidths can be greatly inhibited by minimizing the layout spacing and signal propagation delay, which sheds new light on the radiation-hardened ICs (integrated circuits) design. Studies show that the SET pulsewidths of propagation are not in direct proportion to the LET (linear energy transfer) of incident particles, thus the defining of the LET threshold should be noted when SET/SEU (single event upset) occurs for the radiation-hardened design. The capability of anti-radiation meets the demand when LET is high but some soft errors may occur when LET is low. Therefore, radiation experiments should be focused on evaluating the LET that demonstrates the worst response to the circuit. SET propagation, radiation hardening by design, charge collection, charge share, quenching Citation: Qin J R, Chen S M, Liu B W, et al. Research on single event transient pulse quenching effect in 90 nm CMOS technology.

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Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process

Cited by 27 publications

References 10 publications

Simulation Study of the Single-Event Effects Sensitivity in Nanoscale CMOS for Body-Biasing Circuits

Simulation Study of the Single-Event Effects Sensitivity in Nanoscale CMOS for Body-Biasing Circuits

Design of SET tolerant LC oscillators using distributed bias circuitry

Research on single event transient pulse quenching effect in 90 nm CMOS technology

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