Simulation Study of the Single-Event Effects Sensitivity in Nanoscale CMOS for Body-Biasing Circuits

Qin, Jun-Rui; Chen, Shuming; Guo, Changguo; Du, Yi

doi:10.1109/tdmr.2014.2308592

Cited by 11 publications

(5 citation statements)

References 18 publications

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“…The heavy ion physical model is used to simulate the incident ion. The spatial and temporal distributions of charge around the ion track are modeled using the Gaussian radial profile [4,5,6]. In order to simulate the situation of different energetic particle passes through the semiconductor material, the term linear energy transfer (LET) is typically used to describe the energy loss per unit length of ion track [9].…”

Section: Model Design and Simulation Setupmentioning

confidence: 99%

“…n i is the concentration of IEICE Electronics Express, Vol. 16,No.17,[1][2][3][4][5][6] carriers in pure silicon, and E i is Fermi-level of the intrinsic semiconductor. k 0 is Boltzmann constant, T is temperature.…”

Section: Band Structure Analysismentioning

confidence: 99%

“…Since the heavy ion strike is mainly acts on the bulk region of the transistor, such as substrate and well. The characteristic of this area is an important factor which will influence the SET of transistor [6]. Thus it is necessary to study the physical mechanism of bulk area effect on the SET character of transistors in bulk silicon technology.…”

Section: Introductionmentioning

confidence: 99%

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Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS

Zhao

Peng

Liu

et al. 2019

IEICE Electron. Express

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N-well doping concentration plays an important role in singleevent transient (SET) characteristic of transistors. While adjusting the Nwell doping parameter within a proper range, it has little effect on the basic electrical performance of P-type MOSFET. The physical mechanism of well doping effects on the SET of PMOS is observed. The collapse and recovery of N-well potential, which are the critical factors that influences the SET pulse width, are analyzed by TCAD simulations. The result shows that well doping concentration could affect not only the rate of well potential recover to its equilibrium value, but the potential gradient induced by localized collapse of N-well potential between ion-strike path and source. Energy band analysis is also carried out under the triple well structure, and results show that an increase in well doping concentration will elevate the barrier of reverse-biased P-N junction and therefore cause the accumulation of holes in well, elevating the well potential, and consequently, inhibiting the parasitic bipolar amplification effect.

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Section: Model Design and Simulation Setupmentioning

confidence: 99%

Section: Band Structure Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS

Zhao

Peng

Liu

et al. 2019

IEICE Electron. Express

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“…[7,8] Much work has been done to investigate the pulse quenching in planar CMOS logic circuits. [9][10][11][12] As the feature size of transistor and space between devices scale down, the charge sharing effect (also called the multi-node charge collection) is becoming an important topic in FinFET technology. [13,14] However, to the best of our knowledge, little work has been done on the SET pulse quenching in those novel FinFET devices.…”

Section: Introductionmentioning

confidence: 99%

Effect of supply voltage and body-biasing on single-event transient pulse quenching in bulk fin field-effect-transistor process

Yu¹,

Chen²,

Chen³

et al. 2016

Chinese Phys. B

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Charge sharing is becoming an important topic as the feature size scales down in fin field-effect-transistor (FinFET) technology. However, the studies of charge sharing induced single-event transient (SET) pulse quenching with bulk FinFET are reported seldomly. Using three-dimensional technology computer aided design (3DTCAD) mixed-mode simulations, the effects of supply voltage and body-biasing on SET pulse quenching are investigated for the first time in bulk FinFET process. Research results indicate that due to an enhanced charge sharing effect, the propagating SET pulse width decreases with reducing supply voltage. Moreover, compared with reverse body-biasing (RBB), the circuit with forward body-biasing (FBB) is vulnerable to charge sharing and can effectively mitigate the propagating SET pulse width up to 53% at least. This can provide guidance for radiation-hardened bulk FinFET technology especially in low power and high performance applications.

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“…The academic and industrial research community is carrying out exploratory research into low power consumption SADFF, such as non-volatile magnetic flip-flop based on spintronic devices [11][12][13][14].Until recently, however, all spintronic devices have required ferromagnetic metals, which do not mesh well with current microchip production CMOS process. Fortunately, the body-biasing schematic benefits CMOS digital circuits for both leakage power reduction and switching speed improvement [15][16][17]. But the efficiency of body biasing strongly depends on the device type and operating temperature.…”

Section: Introductionmentioning

confidence: 99%

High-Speed Low-Power Bulk-Controlled Sense-Amplifier D Flip-Flop

Deng

Ning

2015

AMM

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With the development of digital very large scale integrated circuits (VLSI), how to reduce the power dissipation and improve the operation speed are two aspects among the most concerned fields. Based on sense amplifier technology and bulk-controlled technique, this paper proposes a bulk-controlled sense-amplifier D flip-flop (BCSADFF). Firstly, this flip-flop can change the threshold voltage of the NMOS by inputting control signals from the substrate so as to control the operating current. Secondly, the traditional RS flip-flop composed of two NAND gates is improved to a couple of inverters based on pseudo-PMOS dynamic technology. Therefore, the proposed BCSADFF can both effectively reduce the power dissipation and improve the circuit speed. Thirdly, the designed BCSADFF can work normally with ultra-dynamic voltage scaling from 1.8 V to 0.6V for SMIC 0.18-um standard CMOS process. Lastly, the Hspice simulation result shows that, compared with the traditional sense-amplifier D flip-flop (SADFF), the power dissipation of the BCSADFF is significantly reduced under the same operating conditions. When the power supply voltage is 0.9V, the power dissipation and delay of the SADFF is 6.54uW and 0.386ns while that of the proposed BCSADFF is 2.09uW and 0.237ns.

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Simulation Study of the Single-Event Effects Sensitivity in Nanoscale CMOS for Body-Biasing Circuits

Cited by 11 publications

References 18 publications

Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS

Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS

Effect of supply voltage and body-biasing on single-event transient pulse quenching in bulk fin field-effect-transistor process

High-Speed Low-Power Bulk-Controlled Sense-Amplifier D Flip-Flop

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