Comparison of error rates in combinational and sequential logic

Büchner, S.; Baze, M.P.; Brown, DJ; McMorrow, D.; Melinger, Joseph S.

doi:10.1109/23.659037

Cited by 201 publications

(72 citation statements)

References 11 publications

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“…Fig. 1 shows the relative contribution to error rates for combinational and sequential logic as a function of frequency [2]. At higher frequencies, or for advanced technologies, the error rates for combinational logic have started to dominate [2 -5].…”

Section: Introductionmentioning

confidence: 99%

On-Chip Characterization of Single-Event Transient Pulsewidths

Narasimham

Ramachandran

Bhuva

et al. 2006

IEEE Trans. Device Mater. Relib.

132

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Abstract-A new on-chip Single Event Transient (SET) test structure has been developed that can autonomously measure the width of random SET pulses. Simulation results show measurement granularity of 900 ps for a 1.5 µm technology and 65 ps for 0.13 µm technology. Laser tests were used to obtain experimental data on test chips fabricated using 1.5 µm process. Experimental measurements show pulse widths varying from 900 ps to over 3 ns as the laser energy is increased.Index Terms-Single event transient (SET), transient pulse width

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Section: Introductionmentioning

confidence: 99%

On-Chip Characterization of Single-Event Transient Pulsewidths

Narasimham

Ramachandran

Bhuva

et al. 2006

IEEE Trans. Device Mater. Relib.

132

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“…For instance, the minimum pulse width required for propagating a transient fault in SOI has been reduced from 105ps for 350nm to a 40ps for 100nm sizes [5]. Finally, in high frequency systems the occurrence of transient upsets increases linearly with the frequency [6]. Altogether, these facts raise concern on the growing numbers and variety of faults next generation systems must face effectively.…”

Section: Introductionmentioning

confidence: 99%

Increasing the Dependability of VLSI Systems through Early Detection of Fugacious Faults

Espinosa

Andrés

Gil

2015

2015 11th European Dependable Computing Conference (EDCC)

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Abstract-Technology advances provide a myriad of advantages for VLSI systems, but also increase the sensitivity of the combinational logic to different fault profiles. Shorter and shorter faults which up to date had been filtered, named as fugacious faults, require new attention as they are considered a feasible sign of warning prior to potential failures. Despite their increasing impact on modern VLSI systems, such faults are not largely considered today by the safety industry. Their early detection is however critical to enable an early evaluation of potential risks for the system and the subsequent deployment of suitable failure avoidance mechanisms. For instance, the early detection of fugacious faults will provide the necessary means to extend the mission time of a system thanks to the temporal avoidance of aging effects. Because classical detection mechanisms are not suited to cope with such fugacious faults, this paper proposes a method specifically designed to detect and diagnose them. Reported experiments will show the feasibility and interest of the proposal.

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“…A flux of about 13 neutrons/((cm 2 ) × h) reaches ground at sea level, and the flux exponentially increases with altitude [29]. A neutron strike may perturb the transistor state, generating bitflips in memory or a current spike in logic circuits that, if latched, leads to a fault [8,36].…”

Section: Background 21 Transient Errors Effects In Hpcmentioning

confidence: 99%

Experimental and analytical study of Xeon Phi reliability

Oliveira

Pilla

DeBardeleben

et al. 2017

Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis

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We present an in-depth analysis of transient faults effects on HPC applications in Intel Xeon Phi processors based on radiation experiments and high-level fault injection. Besides measuring the realistic error rates of Xeon Phi, we quantify Silent Data Corruption (SDCs) by correlating the distribution of corrupted elements in the output to the application's characteristics. We evaluate the benefits of imprecise computing for reducing the programs' error rate. For example, for HotSpot a 0.5% tolerance in the output value reduces the error rate by 85%.We inject different fault models to analyze the sensitivity of given applications. We show that portions of applications can be graded by different criticalities. For example, faults occurring in the middle of LUD execution, or in the Sort and Tree portions of CLAMR, are more critical than the remaining portions. Mitigation techniques can then be relaxed or hardened based on the criticality of the particular portions.

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Comparison of error rates in combinational and sequential logic

Cited by 201 publications

References 11 publications

On-Chip Characterization of Single-Event Transient Pulsewidths

On-Chip Characterization of Single-Event Transient Pulsewidths

Increasing the Dependability of VLSI Systems through Early Detection of Fugacious Faults

Experimental and analytical study of Xeon Phi reliability

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