HBD layout isolation techniques for multiple node charge collection mitigation

Black, Jeffrey D.; Sternberg, Andrew L.; Alles, Michael L.; Witulski, A.F.; Bhuva, B. L.; Massengill, L.W.; Benedetto, J.M.; Baze, M.P.; Wert, J.L.; Hubert, M.G.

doi:10.1109/tns.2005.860718

Cited by 105 publications

(21 citation statements)

References 2 publications

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“…A more extensive study evaluated the improvement obtained by extending the substrate/well contacts to create "guard contacts" between transistors as well as partitioning the N-well to isolate the PMOS devices. These simulations, as well as actual heavy-ion testing, found that charge collection in PMOS transistors is significantly reduced by adding N+ guard contacts between the transistors in the N-well, but the guard contacts between NMOS transistors and the partitioned well provided little improvement [104]. Unlike the dummy source/drain structures, the guard contacts were of the same type (P or N) as the underlying substrate or well and therefore could not be reverse-biased.…”

Section: Seu-resistant Latch Circuitsmentioning

confidence: 99%

Magnetic Random Access Memory for Embedded Computing

Donohoe¹

2007

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Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing this collection of information. MRAM_II_2007-Final SPONSORING / MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSOR/MONITOR'S ACRONYM(S)Air Force Research Laboratory AFRL/RVSE Space Vehicles Directorate 3550 Aberdeen Ave. SE SPONSOR/MONITOR'S REPORTKirtland AFB, NM 87117-5776 NUMBER(S) AFRL-RV-PS-TR-2007-1196 DISTRIBUTION / AVAILABILITY STATEMENTApproved for public release; distribution is unlimited. (Clearance #VS07-0688) SUPPLEMENTARY NOTESThis report is published in the interest of scientific and technical information exchange. The established procedures for editing reports were not followed for this technical report. ABSTRACTThe goal of this research was to develop an embedded magnetic memory technology to be integrated into Complementary Metal Oxide Semiconductor (CMOS) integrated circuit fabrication process to provide radiation-hard, logic elements and small random-access memories. The goal is not to provide largescale, bulk memory, but latches and flip flops that serve as state and data registers for sequential logic, and configuration registers for configurable logic. The benefits to spacecraft systems include the ability to power-down a subsystem while retaining system state, thus saving energy until the subsystem is required. The subsystem can then be powered-up and begin operating in milliseconds. The technology is based on a unique, PacMan-shaped magnetic tunneling junction (MTJ) cell developed at the University of Idaho. The focus of this research is to refine the PacMan cell to make it practical for integration into CMOS circuits, to develop CMOS circuits that employ the magnetic cells, and to integrate the cells onto a CMOS process. The process produced two circuit designs based on magnetic memory elements: a magnetic latch, and a magnetic shadow memory to serve as a backup to volatile electronic memory. ii University of Idaho report MRAM_II_2007-Final SUBJECT TERMS CMOS, MTJ Cell

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Section: Seu-resistant Latch Circuitsmentioning

confidence: 99%

Magnetic Random Access Memory for Embedded Computing

Donohoe¹

2007

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“…At layout-level, guard rings and guard bands are usually used to sink excess charge away to reduce the produced SET pulse width [2,3]. A layout hardening technique presented by Atkinson et al [4] exploits the pulse quenching effect to limit the pulse origination.…”

Section: Introductionmentioning

confidence: 99%

A DMR logic for mitigating the SET induced soft errors in combinational circuits

Zhang

Yang

et al. 2016

IEICE Electron. Express

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In this paper, a novel dual module redundancy (DMR) logic circuit structure is proposed to harden the standard cells in the large combinational circuits. Three-dimensional TCAD simulation results present that this hardening structure can ultimately eliminate the SET pulse. Based on this DMR logic circuit structure and the layout placement adjustment technique, the partial hardening approach is used to harden the large combination circuits.

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“…take a large percentage of silicon area in modern microprocessors or Systems on Chip (SOC) [4,21]. As the feature size scales down to nano-scale, a charge cloud generated by a single particle may cover multiple transistors, causing multiple bit upsets (MBU) and significantly increasing soft error rate (SER) [5,7]. This is also complicated by charge sharing (i.e.…”

Section: Introductionmentioning

confidence: 99%