A DMR logic for mitigating the SET induced soft errors in combinational circuits

Abstract

In this paper, a novel dual module redundancy (DMR) logic circuit structure is proposed to harden the standard cells in the large combinational circuits. Three-dimensional TCAD simulation results present that this hardening structure can ultimately eliminate the SET pulse. Based on this DMR logic circuit structure and the layout placement adjustment technique, the partial hardening approach is used to harden the large combination circuits.