An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology

Abstract

This paper presents an SEU-resilient 12 T SRAM bitcell. Simulation results demonstrate that it has higher critical charge than the traditional 6 T cell. Alpha and proton testing results validate that it has a lower soft error rate compared to the reference designs for all data patterns and supply voltage levels. The improvement in SEU tolerance is achieved at the expense of 2X area penalty.