As a result of the increasing demand for deep neural network (DNN)-based services, efforts to develop dedicated hardware accelerators for DNNs are growing rapidly. However, while accelerators with high performance and efficiency on convolutional deep neural networks (Conv-DNNs) have been developed, less progress has been made with regards to fullyconnected DNNs (FC-DNNs). In this paper, we propose MATIC (Memory Adaptive Training with In-situ Canaries), a methodology that enables aggressive voltage scaling of accelerator weight memories to improve the energy-efficiency of DNN accelerators. To enable accurate operation with voltage overscaling, MATIC combines the characteristics of destructive SRAM reads with the error resilience of neural networks in a memory-adaptive training process. Furthermore, PVT-related voltage margins are eliminated using bit-cells from synaptic weights as in-situ canaries to track runtime environmental variation. Demonstrated on a low-power DNN accelerator that we fabricate in 65 nm CMOS, MATIC enables up to 60-80 mV of voltage overscaling (3.3× total energy reduction versus the nominal voltage), or 18.6× application error reduction.

With the rising integration levels used to increase digital processing performance, there is a clear need for multiple independent on-chip supplies in order to support per-IP or block power management. Simply adding multiple off-chip DC-DC converters is not only difficult due to supply impedance concerns, but also adds cost to the platform by increasing motherboard size and package complexity. There is therefore a strong motivation to integrate voltage conversion blocks on the silicon chip.The key challenge associated with realizing such integrated converters is achieving high efficiency at the high power densities required by high-performance digital logic. In typical CMOS processes, on-die capacitors have significantly higher Q and energy density and lower cost than on-die inductors, leading to several recent efforts in exploring fully integrated switched-capacitor (SC) DC-DC converters. For example, both [1] and [2] investigated interleaving to reduce the output ripple of fully integrated SC voltage doublers, with [1] demonstrating high efficiency (82%), and [2] showing high power density (~0.5-1.1W/mm 2 ). In this paper, we expand upon these previous designs by demonstrating a fully integrated step-down SC converter capable of achieving high efficiency (81%) at high power density (0.55W/mm 2 ) while supporting a wide range of output voltage levels.Careful analysis of the 4 major loss components of integrated SC converters (Fig. 10.8.1a) is critical to optimizing converter design parameters (particularly switching frequency, f sw ) and hence achieving high efficiency and power density. At low power density, efficiency is largely set by stray capacitance (bottom/top plate), while at high power density, efficiency is set by flying capacitor density and switch speed. Since the converter is targeted at digital loads, it is important to recognize that the minimum output voltage V min sets the performance of the digital blocks . Therefore, the increased load current caused by the converter's output ripple should be included as additional loss [3]. Fortunately, interleaving reduces ripple without impacting V min , and is thus effective in mitigating this loss.As shown in Fig. 10.8.1b, in order to enable variable conversion ratios while maintaining efficiency, the converter is partitioned into multiple standard cells, each consisting of 1 flying capacitor and 5 switches. Conceptually, each standard cell can be configured to operate in series or in parallel with the rest of the cells, leading to a simple physical design strategy that supports variable converter topology. In this demonstration, we group 2 standard cells in a converter unit supporting 3 topologies with conversion ratios of 2/3, 1/2, and 1/3 (1.33V, 1V, and 0.66V with a 2V input). Intermediate voltage levels are generated by controlling f sw and thus the output impedance of the converter [4], which is equivalent to linear regulation off of the ideal voltage.Each converter unit operates in 2 non-overlapping clock phases c1 and c2 (Fig. 10.8.2) with contr...

No abstract

Abstract-Recent advances in neural networks (NNs) exhibit unprecedented success at transforming large, unstructured data streams into compact higher-level semantic information for tasks such as handwriting recognition, image classification, and speech recognition. Ideally, systems would employ near-sensor computation to execute these tasks at sensor endpoints to maximize data reduction and minimize data movement. However, nearsensor computing presents its own set of challenges such as operating power constraints, energy budgets, and communication bandwidth capacities. In this paper, we propose a stochasticbinary hybrid design which splits the computation between the stochastic and binary domains for near-sensor NN applications. In addition, our design uses a new stochastic adder and multiplier that are significantly more accurate than existing adders and multipliers. We also show that retraining the binary portion of the NN computation can compensate for precision losses introduced by shorter stochastic bit-streams, allowing faster run times at minimal accuracy losses. Our evaluation shows that our hybrid stochastic-binary design can achieve 9.8× energy efficiency savings, and application-level accuracies within 0.05% compared to conventional all-binary designs.

No abstract

No abstract

No abstract

No abstract