A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS

Uehlin, John P.; Smith, William Anthony; Pamula, Venkata Rajesh; Pepin, Eric; Perlmutter, Steve I.; Sathe, Visvesh; Rudell, Jacques C.

doi:10.1109/jssc.2020.2991524

Cited by 52 publications

(32 citation statements)

References 28 publications

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“…Alternative techniques that improve the front-end immunity aim to prevent saturation to maintain a linear response [6], or achieve rapid recovery for reduced data loss [7]. Back-end cancellation methods are often applied to digitized signals to reconstruct the neural data or subtract artifacts via adaptive filtering [5], achieving reliable artifact removal at the cost of area and complexity [8].…”

Section: A Conventional Methodsmentioning

confidence: 99%

An Active Microchannel Neural Interface with Artifact Reduction

Habibollahi

Hanzaee

Jiang

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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High-density neural electrodes in microchannel interfaces require in-situ amplification of the neural signals and rejection of high-voltage stimulus pulses leaking to the channel in order to adequately detect neural signals in the presence of concurrent stimulation. This paper presents the design of an active microchannel neural interface in 0.18CMOS employing neural recording and stimulation. To reduce stimulus artifacts, a novel method is proposed that disconnects the recording module during concurrent channel stimulation and automatically applies detection and reduction of stimulus artifacts from adjacent channels using a tunable filter. Simulations show that the method provides at least 54 dB artifact attenuation.

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Section: A Conventional Methodsmentioning

confidence: 99%

An Active Microchannel Neural Interface with Artifact Reduction

Habibollahi

Hanzaee

Jiang

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…This limits these designs to recorder-only implementations, while integrated neuromodulator SoCs require the usage of HV-capable technology nodes at the cost of a performance penalty in the recorder. One possible solution to this issue was published in [32], where a stimulation voltage compliance of ±11 V was achieved by using H-bridge stimulators. The issue of low voltage tolerance of individual devices (1.2 V, 65 nm process) was tackled by stacking LV-devices in the adaptive resonant HV charge pumps.…”

Section: µV Rms In Both Bandsmentioning

confidence: 99%

A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip

Reich

Sporer

Haas

et al. 2021

IEEE J. Solid-State Circuits

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This paper presents the integration of a 32-channel neuromodulation system on chip (SoC) which is developed for chronic implantation in humans. The ASIC offers low noise recording, a state-of-the-art (SotA) neurostimulator capable of both current and voltage controlled stimulation with highvoltage compliance, on-chip 16-bit data digitization as well as safety features like electrode impedance estimation and charge balancing. The chip communicates through two distinct SPI interfaces for independent command and data transfer. Thus, the developed system constitutes a fully digital, bidirectional 32channel interface to the brain.

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“…The alternative is to share a single AFE between different electrodes at different time slots, while keeping the same throughput rate per channel, as shown in Fig. 1(b) [6], [12]- [16]. This approach clearly favours area reduction and essentially eliminates the mismatch problems of multi-channel topologies [17], thus paving the way to delta encode signals recorded from different sites.…”

Section: Introductionmentioning

confidence: 99%

A 32-Channel Time-Multiplexed Artifact-Aware Neural Recording System

Perez-Prieto

Rodríguez-Vázquez

Álvarez‐Dolado

et al. 2021

IEEE Trans. Biomed. Circuits Syst.

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This paper presents a low-power, low-noise microsystem for the recording of neural local field potentials or intracranial electroencephalographic signals. It features 32 timemultiplexed channels at the electrode interface and offers the possibility to spatially delta encode data to take advantage of the large correlation of signals captured from nearby channels. The circuit also implements a mixed-signal voltage-triggered autoranging algorithm which allows to attenuate large interferers in digital domain while preserving neural information. This effectively increases the system dynamic range and avoids the onset of saturation. A prototype, fabricated in a standard 180 nm CMOS process, has been experimentally verified in-vitro with cellular cultures of primary cortical neurons from mice. The system shows an integrated input-referred noise in the 0.5-200 Hz band of 1.4 µVrms for a spot noise of about 85 nV/ √ Hz. The system draws 1.5 µW per channel from 1.2 V supply and obtains 71 dB + 26 dB dynamic range when the artifact-aware autoranging mechanism is enabled, without penalising other critical specifications such as crosstalk between channels or commonmode and power supply rejection ratios.

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A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS

Cited by 52 publications

References 28 publications

An Active Microchannel Neural Interface with Artifact Reduction

An Active Microchannel Neural Interface with Artifact Reduction

A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip

A 32-Channel Time-Multiplexed Artifact-Aware Neural Recording System

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