2017 Symposium on VLSI Circuits 2017
DOI: 10.23919/vlsic.2017.8008470
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A scalable, highly-multiplexed delta-encoded digital feedback ECoG recording amplifier with common and differential-mode artifact suppression

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Cited by 34 publications
(21 citation statements)
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“…A current buffer with high-voltage supply supported the insufficient voltage of the in-chip DAC to apply electrical stimulation in animal testing. The artifact-tolerant method to prevent DC offset from the electrode was required in real in vivo testing, where on-chip solutions were also provided by previous works [52], [53]. Without a designed on-chip, the DC blockage (high-pass filter with bias, corner frequency: 0.05 Hz) with passive element was added at the input stage of integrated system board to prevent the DC offset.…”
Section: Verification Of Epilepsy Suppression By Wpssocmentioning
confidence: 99%
“…A current buffer with high-voltage supply supported the insufficient voltage of the in-chip DAC to apply electrical stimulation in animal testing. The artifact-tolerant method to prevent DC offset from the electrode was required in real in vivo testing, where on-chip solutions were also provided by previous works [52], [53]. Without a designed on-chip, the DC blockage (high-pass filter with bias, corner frequency: 0.05 Hz) with passive element was added at the input stage of integrated system board to prevent the DC offset.…”
Section: Verification Of Epilepsy Suppression By Wpssocmentioning
confidence: 99%
“…As a result, neural recording designs have primarily focused on optimizing power efficiency to extend battery life, reduce wireless power harvesting requirements, or minimize heat dissipation [28][29][30][31]. As recording systems scale to higher channel counts (>1000), power-efficient design is further exacerbated by tight area constraints [32][33][34] and high communication data rates [35].…”
Section: Design For Front-end Artifact Immunitymentioning
confidence: 99%
“…Another approach is to reduce the requirement for a large dynamic range by subtracting, using hardware methods, a model of the artifact at the input during stimulation to keep signals within a smaller range (Figure 3f). The model of the artifact is learned through template building [32,37], filtering the stimulation pulse [38 ], or creating a replica artifact signal [39]. This technique holds promise, but can degrade the signal-to-noise ratio (SNR) of the underlying neural signal [38 ].…”
Section: Design For Front-end Artifact Immunitymentioning
confidence: 99%
“…This led to the choice of implementing the 5-bit fine offset correction DAC by changing the size of the input pair [ 28 ], resulting in low area overhead and fast settling (<166 ns). An alternative would be a capacitive DAC at the G M input nodes [ 18 ], but this approach would require capacitive coupling between the LNA and G M amplifiers, and the input pair DAC is a simpler implementation.…”
Section: Rapidly Multiplexed Neural Recording Circuit Architecturementioning
confidence: 99%
“…However, rapid multiplexing directly at the electrodes raises challenges related to electrode offsets and aliasing of high-frequency noise. These challenges have been shown to be tractable for non-penetrating microelectrode arrays used in electrocorticography (ECoG) [ 18 , 19 ], but these low-impedance arrays measure average neural activity from large groups of neurons and generally do not provide the spatial or temporal resolution needed to observe action potentials.…”
Section: Introductionmentioning
confidence: 99%