A 0.0023 mm$^2$/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression

Uehlin, John P.; Smith, William Anthony; Pamula, Venkata Rajesh; Perlmutter, Steve I.; Rudell, Jacques C.; Sathe, Visvesh

doi:10.1109/tbcas.2019.2963174

Cited by 33 publications

(20 citation statements)

References 42 publications

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“…Table I summarizes the performance of the proposed neural recording front-end and compares it with the previous works [4], [7]- [10], [13]- [15]. The silicon footprint is four times smaller than the smallest AC-coupled front-end reported, and it is comparable to the recent DC-coupled ones.…”

Section: Measurement Resultsmentioning

confidence: 95%

“…The silicon footprint is four times smaller than the smallest AC-coupled front-end reported, and it is comparable to the recent DC-coupled ones. The power consumption is the lowest [7] JSSC'15 [13] JSSC'17 [9] JSSC'18 [4] SSCL'18 [14] JSSC'18 [8] TBCAS'19 [15] TBCAS'20 [10] This work 2 On-chip decimation filter. 3 Off-chip decimation filter.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…1(d ... rail-to-rail cancellation at the cost of reduced input impedance and increased noise at high sampling rates [9], which is also the case when the electrodes are multiplexed into a shared front-end (Fig. 1(e)) [10]. Moreover, the injection of switching currents into the neural tissue raises safety concerns which has not yet been addressed.…”

Section: Introductionmentioning

confidence: 99%

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An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm²×fJ/conv-step Efficiency and 0.97 NEF

Uran

Leblebici

Emami

et al. 2020

IEEE Solid-State Circuits Lett.

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This paper presents an energy-and-area-efficient ACcoupled front-end for multichannel recording of wideband neural signals.The proposed unit conditions local field and action potentials using an inverter-based capacitively-coupled low-noise amplifier, followed by a perchannel 10-bit asynchronous SAR ADC. The adaptation of unit-length capacitors minimizes the ADC area and relaxes the amplifier gain so that small coupling capacitors can be integrated. The prototype in 65nm CMOS achieves 4× smaller area and 3× higher energy-area efficiency compared to the state of the art with 164 µm×40 µm footprint and 0.78 mm 2 ×fJ/conv-step energy-area figure of merit. The measured 0.65 µW power consumption and 3.1 µVrms input-referred noise within 1Hz-10kHz bandwidth correspond to a noise efficiency factor of 0.97. Index Terms-AC coupling, front-end, inverter-based amplifier, monotonic switching, neural recording, successive approximation register analog-to-digital-converter, unit length capacitor.

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Section: Measurement Resultsmentioning

confidence: 95%

Section: Measurement Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm²×fJ/conv-step Efficiency and 0.97 NEF

Uran

Leblebici

Emami

et al. 2020

IEEE Solid-State Circuits Lett.

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“…Different researchers have focused on different features in their design. For example, some studies have focused on the low power of the amplifier [11,12], some have pursued low noise [13,14,15], while others have paid more attention to the NEF [16,17,18,19], high input impedance [20,21], little distortion [22,23,24] and small area [25,26]. A tradeoff exists between power, noise and area and balancing these performances in design is important.…”

Section: Discussionmentioning

confidence: 99%

A Robust 4-channel Micro-power Low-noise Neural Recording Amplifier for Hippocampal Cognitive Prosthesis

Ni¹,

Han²,

Lei³

et al. 2020

Preprint

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Background: Recording of electrical activity of neurons is indispensable for decoding the information in the brain. The amplitude of signals recorded by electrodes is small, and it must be amplified to the level that can be digitalized by the analog-to-digital convert (ADC). A micro-power low-noise neural recording amplifier is indispensable for implant hippocampal cognitive prosthesis. When the process turns into deep submicron, the gate leakage current of the metal oxide semiconductor (MOS) transistor becomes larger and mismatch between devices becomes worsen. It is necessary to keep the neural amplifier robust in all process corners. Methods: The proposed circuit is a two-stage amplifier which can achieve a good trade-off between power consumption and noise. Four second-stage amplifiers share a common reference amplifier to reduce area and power consumption. A pseudo-resistor with high resistance is utilized to realize a very-low frequency high pass corner without external components. In order to minimize process variation, a bulk-compensated (BC) technique is adopted to maintain adequate tolerance in all corner case. Results: The 4-channel neural amplifier is designed and fabricated in a 40 nm standard complementary metal oxide semiconductor (CMOS) process. It achieves a mid-band gain of 54 dB, a bandwidth of 70 Hz to 7.7 kHz, a total input-referred noise of 3.2 μVrms , and a Noise Efficiency Factor (NEF) of 3.3 while consuming 4.68 µW from the 1.1 V supply. The core area of one channel is only 0.032 mm 2 . Conclusion: A 4-channel integrated neural recording amplifier chip with bias-compensated circuits is presented in this paper. Extensive simulations insure that the design is “center”. The chip layout is verified using design rules check (DRC) and layout versus schematic (LVS) design check with the help of verification tools. Test results shows that it is less sensitive to process variation and consumes less power compared with amplifier without bulk-compensated circuit. This makes the design robust and uniquely appropriate for low-power implant application.

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“…This reduces the occupation area per channel and ignores mismatch between recording channels, potentially making the power consumption per channel lower than in conventional topologies (a further breakdown of the AFE time-division-multiplexing specifications and architectures is provided in section 6). For instance, it can be observed in Figure 6B how the TDM AFE reported in Uehlin et al (2020) shows one of the most promising results in terms of area and noise equivalent bandwidth (NEB), which is defined as the bandwidth of a brickwall filter which produce same integrated noise power as that of the analyzed system, for this kind of topologies. The main drawback of these topologies relies on the requirement of a high-bandwidth LNA (HB LNA) to fast-multiplex all the channels, which significantly increases power consumption and in-band noise due to aliasing (Sharma et al, 2018).…”

Section: Time-division-multiplexing Afe Topologymentioning

confidence: 94%

Recording Strategies for High Channel Count, Densely Spaced Microelectrode Arrays

Perez-Prieto

Delgado‐Restituto

2021

Front. Neurosci.

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Neuroscience research into how complex brain functions are implemented at an extra-cellular level requires in vivo neural recording interfaces, including microelectrodes and read-out circuitry, with increased observability and spatial resolution. The trend in neural recording interfaces toward employing high-channel-count probes or 2D microelectrodes arrays with densely spaced recording sites for recording large neuronal populations makes it harder to save on resources. The low-noise, low-power requirement specifications of the analog front-end usually requires large silicon occupation, making the problem even more challenging. One common approach to alleviating this consumption area burden relies on time-division multiplexing techniques in which read-out electronics are shared, either partially or totally, between channels while preserving the spatial and temporal resolution of the recordings. In this approach, shared elements have to operate over a shorter time slot per channel and active area is thus traded off against larger operating frequencies and signal bandwidths. As a result, power consumption is only mildly affected, although other performance metrics such as in-band noise or crosstalk may be degraded, particularly if the whole read-out circuit is multiplexed at the analog front-end input. In this article, we review the different implementation alternatives reported for time-division multiplexing neural recording systems, analyze their advantages and drawbacks, and suggest strategies for improving performance.

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A 0.0023 mm$^2$/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression

Cited by 33 publications

References 42 publications

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm²×fJ/conv-step Efficiency and 0.97 NEF

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm²×fJ/conv-step Efficiency and 0.97 NEF

A Robust 4-channel Micro-power Low-noise Neural Recording Amplifier for Hippocampal Cognitive Prosthesis

Recording Strategies for High Channel Count, Densely Spaced Microelectrode Arrays

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A 0.0023 mm$^2$/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression

Cited by 33 publications

References 42 publications

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm2×fJ/conv-step Efficiency and 0.97 NEF

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm2×fJ/conv-step Efficiency and 0.97 NEF

A Robust 4-channel Micro-power Low-noise Neural Recording Amplifier for Hippocampal Cognitive Prosthesis

Recording Strategies for High Channel Count, Densely Spaced Microelectrode Arrays

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Product

Resources

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An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm²×fJ/conv-step Efficiency and 0.97 NEF

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm²×fJ/conv-step Efficiency and 0.97 NEF