This paper presents an energy-and-area-efficient ACcoupled front-end for multichannel recording of wideband neural signals.The proposed unit conditions local field and action potentials using an inverter-based capacitively-coupled low-noise amplifier, followed by a perchannel 10-bit asynchronous SAR ADC. The adaptation of unit-length capacitors minimizes the ADC area and relaxes the amplifier gain so that small coupling capacitors can be integrated. The prototype in 65nm CMOS achieves 4× smaller area and 3× higher energy-area efficiency compared to the state of the art with 164 µm×40 µm footprint and 0.78 mm 2 ×fJ/conv-step energy-area figure of merit. The measured 0.65 µW power consumption and 3.1 µVrms input-referred noise within 1Hz-10kHz bandwidth correspond to a noise efficiency factor of 0.97. Index Terms-AC coupling, front-end, inverter-based amplifier, monotonic switching, neural recording, successive approximation register analog-to-digital-converter, unit length capacitor.
Next generation invasive neural interfaces require fully implantable wireless systems that can record from a large number of channels simultaneously. However, transferring the recorded data from the implant to an external receiver emerges as a significant challenge due to the high throughput. To address this challenge, this paper presents a neural recording system-on-chip that achieves high resource and wireless bandwidth efficiency by employing on-chip feature extraction. An energy-area efficient 10-bit 20 kS/s front-end amplifies and digitizes the neural signals within the LFP and AP bands. The raw data from each channel is decomposed into spectral features using a Compressed Hadamard Transform (CHT) processor. The selection of the features to be computed is tailored through a machine learning algorithm, such that the overall data rate is reduced by 80% without compromising classification performance. Moreover, the CHT feature extractor allows waveform reconstruction on the receiver side for monitoring or additional post-processing. The proposed approach was validated through in vivo and offline experiments. The prototype fabricated in 65nm CMOS also includes wireless power and data receiver blocks to demonstrate the energy and area efficiency of the complete system. The overall signal chain consumes 2.6 µW and occupies 0.021 mm 2 per channel, pointing towards its feasibility for thousand-channel single-die neural recording systems.
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