A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm² at 81% efficiency

Abstract

With the rising integration levels used to increase digital processing performance, there is a clear need for multiple independent on-chip supplies in order to support per-IP or block power management. Simply adding multiple off-chip DC-DC converters is not only difficult due to supply impedance concerns, but also adds cost to the platform by increasing motherboard size and package complexity. There is therefore a strong motivation to integrate voltage conversion blocks on the silicon chip.The key challenge associated with realizing such integrated converters is achieving high efficiency at the high power densities required by high-performance digital logic. In typical CMOS processes, on-die capacitors have significantly higher Q and energy density and lower cost than on-die inductors, leading to several recent efforts in exploring fully integrated switched-capacitor (SC) DC-DC converters. For example, both [1] and [2] investigated interleaving to reduce the output ripple of fully integrated SC voltage doublers, with [1] demonstrating high efficiency (82%), and [2] showing high power density (~0.5-1.1W/mm 2 ). In this paper, we expand upon these previous designs by demonstrating a fully integrated step-down SC converter capable of achieving high efficiency (81%) at high power density (0.55W/mm 2 ) while supporting a wide range of output voltage levels.Careful analysis of the 4 major loss components of integrated SC converters (Fig. 10.8.1a) is critical to optimizing converter design parameters (particularly switching frequency, f sw ) and hence achieving high efficiency and power density. At low power density, efficiency is largely set by stray capacitance (bottom/top plate), while at high power density, efficiency is set by flying capacitor density and switch speed. Since the converter is targeted at digital loads, it is important to recognize that the minimum output voltage V min sets the performance of the digital blocks . Therefore, the increased load current caused by the converter's output ripple should be included as additional loss [3]. Fortunately, interleaving reduces ripple without impacting V min , and is thus effective in mitigating this loss.As shown in Fig. 10.8.1b, in order to enable variable conversion ratios while maintaining efficiency, the converter is partitioned into multiple standard cells, each consisting of 1 flying capacitor and 5 switches. Conceptually, each standard cell can be configured to operate in series or in parallel with the rest of the cells, leading to a simple physical design strategy that supports variable converter topology. In this demonstration, we group 2 standard cells in a converter unit supporting 3 topologies with conversion ratios of 2/3, 1/2, and 1/3 (1.33V, 1V, and 0.66V with a 2V input). Intermediate voltage levels are generated by controlling f sw and thus the output impedance of the converter [4], which is equivalent to linear regulation off of the ideal voltage.Each converter unit operates in 2 non-overlapping clock phases c1 and c2 (Fig. 10.8.2) with contr...

Optimization of a multi-target voltages switched capacitor converter

“…The result shows that the proposed SCC dramatically improves the efficiency at low output voltages. Specifically, the SCC efficiency is improved by 16% in the vicinity of V DD =200mV as compared to the one using a conventional 9 switch topology [6], [8] while remaining with the same efficiency at the rest of the range. The SCC achieves a peak efficiency of 87% at V DD =0.53V with 200μA load current.…”

“…The SCC is designed to implement 4 different conversion ratios, excluding the trivial case G=1. The reader is referred to [6] and [8] for a detailed analysis of the ordinary conversion ratios and their corresponding topologies. When the circuit is supposed to operate with G=1/4, essentially it consists of three subcircuits extended over three non-overlapping time sessions {Ф 1 ,Ф 2 ,Ф 3 }.…”

“…These studies have shown that the efficiency of multiple conversion ratios SCC can be maintained effective over wider input voltage range than that of a single topology converter. It is shown that a combination of two standard divide by two SCC cells can support two additional topologies, which provide 2/3 and 1/3 conversion ratios [8]. This circuit and its variants were systematically designed in numerous works, utilizing one or more of its possible conversion ratios.…”

“…This circuit and its variants were systematically designed in numerous works, utilizing one or more of its possible conversion ratios. For example, an interleaved SCC structure partitioned into multiple circuits to reduce the input current and output voltage ripples has been explored in [8].…”

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

“…The two parameters are the average portion of time spent in active mode and the average K aging during active mode. The range and granularities between the minimum and maximum discrete levels of the self-tuning parameters (supply voltage, clock frequency, and cooling) needed to achieve the maximized self-tuning benefits are supported by state-of-the-art commercial hardware solutions (e.g., [32], [37], [41], [58], [59]). The power and area overheads for the regulators were also shown to be minimal.…”