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Emerging applications in brain-machine interface systems require high-resolution, chronic multisite cortical recordings, which cannot be obtained with existing technologies due to high power consumption, high invasiveness, or inability to transmit data wirelessly. In this paper, we describe a microsystem based on electrocorticography (ECoG) that overcomes these difficulties, enabling chronic recording and wireless transmission of neural signals from the surface of the cerebral cortex. The device is comprised of a highly flexible, high-density, polymer-based 64-channel electrode array and a flexible antenna, bonded to 2.4 mm × 2.4 mm CMOS integrated circuit (IC) that performs 64-channel acquisition, wireless power and data transmission. The IC digitizes the signal from each electrode at 1 kS/s with 1.2 μV input referred noise, and transmits the serialized data using a 1 Mb/s backscattering modulator. A dual-mode power-receiving rectifier reduces data-dependent supply ripple, enabling the integration of small decoupling capacitors on chip and eliminating the need for external components. Design techniques in the wireless and baseband circuits result in over 16× reduction in die area with a simultaneous 3× improvement in power efficiency over the state of the art. The IC consumes 225 μW and can be powered by an external reader transmitting 12 mW at 300 MHz, which is over 3× lower than IEEE and FCC regulations.

This paper provides a perspective on progress toward realization of efficient, fully integrated dc-dc conversion and regulation functionality in CMOS platforms. In providing a comparative assessment between the inductor-based and switchedcapacitor approaches, the presentation reviews the salient features in effectiveness in utilization of switch technology and in use and implementation of passives. The analytical conclusions point toward the strong advantages of the switched-capacitor (SC) approach with respect to both switch utilization and much higher energy densities of capacitors versus inductors. The analysis is substantiated with a review of recently developed and published integrated dc-dc converters of both the inductor-based and SC types.Index Terms-Charge-pump, high power density, power supply on chip, switched-capacitor (SC) dc-dc converters. I. INTRODUCTIONT HE demand for integrated power conversion, regulation, and management functions has progressed along with advances in computing, communicating, and other integrated circuit technologies. Nevertheless, efficient integrated power conversion is now at its infancy in relation to the maturing development of the system-on-chip (SOC) functions that would be best served by such converters. Since present day multicore processors dissipate power in the range of 1 W/mm 2 , and would also ideally utilize many independently controlled voltage rails, a target benchmark is an integrated dc-dc conversion and regulation design that 1) handles about 10 W/mm 2 1 ; 2) steps down from a conveniently chosen voltage above typical CMOS core operating voltages; 3) provides high efficiency over a wide load and voltage range; 4) provides tight regulation; and 5) is highly scalable for granular implementation. Although there are now promising paths toward this set of goals, with both Manuscript

An integrated five-output single-inductor multiple-output dc-dc converter with ordered power-distributive control (OPDC) in a 0.5 m Bi-CMOS process is presented. The converter has four main positive boost outputs programmable from +5 V to +12 V and one dependent negative output ranged from 12 V to 5 V. A maximum efficiency of 80.8% is achieved at a total output power of 450 mW, with a switching frequency of 700 kHz. The performance of the converter as a commercial product is successfully verified with a new control method and proposed circuits, including a full-waveform inductor-current sensing circuit, a variation-free frequency generator, and an in-rush-current-free soft-start method. With simplicity, flexibility, and reliability, the design enables shorter time-to-market in future extensions with more outputs and different operation requirements.

With the rising integration levels used to increase digital processing performance, there is a clear need for multiple independent on-chip supplies in order to support per-IP or block power management. Simply adding multiple off-chip DC-DC converters is not only difficult due to supply impedance concerns, but also adds cost to the platform by increasing motherboard size and package complexity. There is therefore a strong motivation to integrate voltage conversion blocks on the silicon chip.The key challenge associated with realizing such integrated converters is achieving high efficiency at the high power densities required by high-performance digital logic. In typical CMOS processes, on-die capacitors have significantly higher Q and energy density and lower cost than on-die inductors, leading to several recent efforts in exploring fully integrated switched-capacitor (SC) DC-DC converters. For example, both [1] and [2] investigated interleaving to reduce the output ripple of fully integrated SC voltage doublers, with [1] demonstrating high efficiency (82%), and [2] showing high power density (~0.5-1.1W/mm 2 ). In this paper, we expand upon these previous designs by demonstrating a fully integrated step-down SC converter capable of achieving high efficiency (81%) at high power density (0.55W/mm 2 ) while supporting a wide range of output voltage levels.Careful analysis of the 4 major loss components of integrated SC converters (Fig. 10.8.1a) is critical to optimizing converter design parameters (particularly switching frequency, f sw ) and hence achieving high efficiency and power density. At low power density, efficiency is largely set by stray capacitance (bottom/top plate), while at high power density, efficiency is set by flying capacitor density and switch speed. Since the converter is targeted at digital loads, it is important to recognize that the minimum output voltage V min sets the performance of the digital blocks . Therefore, the increased load current caused by the converter's output ripple should be included as additional loss [3]. Fortunately, interleaving reduces ripple without impacting V min , and is thus effective in mitigating this loss.As shown in Fig. 10.8.1b, in order to enable variable conversion ratios while maintaining efficiency, the converter is partitioned into multiple standard cells, each consisting of 1 flying capacitor and 5 switches. Conceptually, each standard cell can be configured to operate in series or in parallel with the rest of the cells, leading to a simple physical design strategy that supports variable converter topology. In this demonstration, we group 2 standard cells in a converter unit supporting 3 topologies with conversion ratios of 2/3, 1/2, and 1/3 (1.33V, 1V, and 0.66V with a 2V input). Intermediate voltage levels are generated by controlling f sw and thus the output impedance of the converter [4], which is equivalent to linear regulation off of the ideal voltage.Each converter unit operates in 2 non-overlapping clock phases c1 and c2 (Fig. 10.8.2) with contr...

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Of the different flat panel displays that can meet the increasing requirements of customers, the active matrix OLED (AMOLED) display is a strong candidate for mobile applications owing to its high resolution, low power consumption and low cost. AMOLED panels, however, usually require multiple power supplies with different regulated voltages. Therefore, step-up switching converters that can supply multiple outputs for this application are important.A single inductor bipolar output (SIBO) converter, shown in Fig. 7.4.1, is presented in this paper to power an AMOLED display for TDMA (GSM) mobile sets, which requires both positive and negative voltages with a gap of 10 to 12V. This converter reduces the overall size and cost of a mobile set. The most critical specification for this application is the line transient response of the positive supply, V OP , which can seriously affect the display by changing V gs of M p4 if it is not fast enough, thus changing the current I OP through the AMOLED. Based on experimentally verified data, the average variation of V OP should be strictly less than 4mV within 51.2µs of a 0.5V fluctuation in the battery voltage, V g , to avoid visible flicker on the display as illustrated in Fig. 7.4.1. Its switching ripple should also be under 30mV for a clean image. However, for the negative output V ON , its variation only affects V ds of M p4 , and hence, its line transient and ripple specifications are not as severe. Because of the stringent requirements for V OP , some chipmakers have attempted to obtain the V OP with an LDO [1] regulator, which creates a trade-off between reduced efficiency and increased cost and area.The converter in Fig. 7.4.1 is a combination of two converters: V OP is obtained from a boost operation employing modified comparator control (MCC) and V ON from a charge-pump circuit with PIcontrol. The control of the power switches is simplified compared to the topologies reported in [2] by delivering charge to all outputs at every switching cycle with priority given to V OP . The charge remaining after transferring charge to V OP is used to control the PWM signal for M n1 . Therefore, the effect of battery voltage fluctuations can be seen on V ON but is very small on V OP since V OP is controlled by a comparator while V ON is controlled by a PI loop. An additional high voltage output V H (= |V ON | + V D1 ) is intentionally generated to supply all gate drivers and to bias the bodies of the power PMOS transistors to reduce the sizes of the switches. The freewheeling switch M p3 is active in the discontinuous-conduction mode (DCM) with the zero-inductor-current detection technique reported in [3]. Consequently, the size and the conduction loss of M p3 are smaller than those of the one in the converter of [4]. .4.3 shows the peak current sensing method used in this converter. The circuit can accurately sense the peak inductor current I peak both in DCM and CCM. Normally, I peak is obtained from the on-voltage across M n1 (in Fig. 7.4.1). However, in this SIBO, the curren...

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