Analysis methods are developed that fully determine a switched-capacitor (SC) dc-dc converter's steady-state performance through evaluation of its output impedance. This analysis method has been verified through simulation and experimentation. The simple formulation developed permits optimization of the capacitor sizes to meet a constraint such as a total capacitance or total energy storage limit, and also permits optimization of the switch sizes subject to constraints on total switch conductances or total switch volt-ampere (V-A) products. These optimizations then permit comparison among several switched-capacitor topologies, and comparisons of SC converters with conventional magnetic-based dc-dc converter circuits, in the context of various application settings. Significantly, the performance (based on conduction loss) of a ladder-type converter is found to be superior to that of a conventional magnetic-based converter for medium to high conversion ratios.

Analysis methods are developed that fully determine a switched-capacitor (SC) dc-dc converter's steady-state performance through evaluation of its output impedance. The simple formulation developed permits optimization of the capacitor sizes to meet a constraint such as a total capacitance or total energy storage limit, and also permits optimization of the switch sizes subject to constraints on total switch conductances or total switch volt-ampere (V-A) products. These optimizations then permit comparison among the switched-capacitor topologies, and comparisons of SC converters with conventional magnetic-based dc-dc converter circuits, in the context of various application settings. Significantly, the performance (based on conduction loss) of a ladder-type converter is found to be superior to that of a conventional boost converter for medium to high conversion ratios.

This paper discusses the theory and implementation of a class of distributed power converters for photovoltaic (PV) energy optimization. Resonant switched-capacitor converters are configured in parallel with strings of PV cells at the sub-module level to improve energy capture in the event of shading or mismatch. The converters operate in a parallel-ladder architecture, enforcing voltage ratios among strings of cells at terminals normally connected to bypass diodes. The balancing function extends from the sub-module level to the entire series string through a dual-core cable and connector. The parallel configuration allows converters to handle only mismatch power and turn off if there is no mismatch in the array. Measurement results demonstrate insertion loss below 0.1% and effective conversion efficiency above 99% for short-circuit current mismatch gradients up to 40%. The circuit implementation eliminates large power magnetic components, achieving a vertical footprint less than 6 mm. The merits of a resonant topology are compared to a switched-capacitor topology.Index Terms-Maximum power point tracking (MPPT), microinverter, resonant converter, solar energy, switched-capacitor.

While they are only capable of a finite number of conversion ratios, SC converters can support a higher power density compared with traditional converters for a given conversion ratio. Finally, through simple control methods, regulation over many magnitudes of output power is possible while maintaining high efficiency.A complete, detailed methodology for SC converter analysis, optimization and implementation is derived. These methods specify device choices and sizing for each capacitor and switch in the circuit, along with the relative sizing between switches and capacitors. This method is advantageous over previously-developed analysis methods because of its simplicity and the intuition it lends towards the design of SC converters. The strengths and weaknesses of numerous topologies are compared amongst themselves and with magnetics-1 based converters. These methods are incorporated into a MATLAB tool for converter design.This design methodology is applied to three varied applications for SC converters. First, a high-voltage hybrid converter for an autonomous micro air vehicle is described. This converter, weighing less than 150mg, creates a supply of 200V from a single lithium-ion cell (3.7V) to supply the aircraft's actuators. Second, a power-management integrated circuit (IC) is presented for a wireless sensor node. This IC, with a target quiescent current of 1 µA, supplies the system voltages of the PicoCube wireless sensor node. Finally, the initial design of a high-current-density SC voltage regulator is presented for low-footprint microprocessor applications.Professor Seth R. Sanders Dissertation Committee Chair 2

This paper provides a perspective on progress toward realization of efficient, fully integrated dc-dc conversion and regulation functionality in CMOS platforms. In providing a comparative assessment between the inductor-based and switchedcapacitor approaches, the presentation reviews the salient features in effectiveness in utilization of switch technology and in use and implementation of passives. The analytical conclusions point toward the strong advantages of the switched-capacitor (SC) approach with respect to both switch utilization and much higher energy densities of capacitors versus inductors. The analysis is substantiated with a review of recently developed and published integrated dc-dc converters of both the inductor-based and SC types.Index Terms-Charge-pump, high power density, power supply on chip, switched-capacitor (SC) dc-dc converters. I. INTRODUCTIONT HE demand for integrated power conversion, regulation, and management functions has progressed along with advances in computing, communicating, and other integrated circuit technologies. Nevertheless, efficient integrated power conversion is now at its infancy in relation to the maturing development of the system-on-chip (SOC) functions that would be best served by such converters. Since present day multicore processors dissipate power in the range of 1 W/mm 2 , and would also ideally utilize many independently controlled voltage rails, a target benchmark is an integrated dc-dc conversion and regulation design that 1) handles about 10 W/mm 2 1 ; 2) steps down from a conveniently chosen voltage above typical CMOS core operating voltages; 3) provides high efficiency over a wide load and voltage range; 4) provides tight regulation; and 5) is highly scalable for granular implementation. Although there are now promising paths toward this set of goals, with both Manuscript

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With the rising integration levels used to increase digital processing performance, there is a clear need for multiple independent on-chip supplies in order to support per-IP or block power management. Simply adding multiple off-chip DC-DC converters is not only difficult due to supply impedance concerns, but also adds cost to the platform by increasing motherboard size and package complexity. There is therefore a strong motivation to integrate voltage conversion blocks on the silicon chip.The key challenge associated with realizing such integrated converters is achieving high efficiency at the high power densities required by high-performance digital logic. In typical CMOS processes, on-die capacitors have significantly higher Q and energy density and lower cost than on-die inductors, leading to several recent efforts in exploring fully integrated switched-capacitor (SC) DC-DC converters. For example, both [1] and [2] investigated interleaving to reduce the output ripple of fully integrated SC voltage doublers, with [1] demonstrating high efficiency (82%), and [2] showing high power density (~0.5-1.1W/mm 2 ). In this paper, we expand upon these previous designs by demonstrating a fully integrated step-down SC converter capable of achieving high efficiency (81%) at high power density (0.55W/mm 2 ) while supporting a wide range of output voltage levels.Careful analysis of the 4 major loss components of integrated SC converters (Fig. 10.8.1a) is critical to optimizing converter design parameters (particularly switching frequency, f sw ) and hence achieving high efficiency and power density. At low power density, efficiency is largely set by stray capacitance (bottom/top plate), while at high power density, efficiency is set by flying capacitor density and switch speed. Since the converter is targeted at digital loads, it is important to recognize that the minimum output voltage V min sets the performance of the digital blocks . Therefore, the increased load current caused by the converter's output ripple should be included as additional loss [3]. Fortunately, interleaving reduces ripple without impacting V min , and is thus effective in mitigating this loss.As shown in Fig. 10.8.1b, in order to enable variable conversion ratios while maintaining efficiency, the converter is partitioned into multiple standard cells, each consisting of 1 flying capacitor and 5 switches. Conceptually, each standard cell can be configured to operate in series or in parallel with the rest of the cells, leading to a simple physical design strategy that supports variable converter topology. In this demonstration, we group 2 standard cells in a converter unit supporting 3 topologies with conversion ratios of 2/3, 1/2, and 1/3 (1.33V, 1V, and 0.66V with a 2V input). Intermediate voltage levels are generated by controlling f sw and thus the output impedance of the converter [4], which is equivalent to linear regulation off of the ideal voltage.Each converter unit operates in 2 non-overlapping clock phases c1 and c2 (Fig. 10.8.2) with contr...

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