Analysis and Optimization of Switched-Capacitor DC–DC Converters

Abstract

Analysis methods are developed that fully determine a switched-capacitor (SC) dc-dc converter's steady-state performance through evaluation of its output impedance. This analysis method has been verified through simulation and experimentation. The simple formulation developed permits optimization of the capacitor sizes to meet a constraint such as a total capacitance or total energy storage limit, and also permits optimization of the switch sizes subject to constraints on total switch conductances or total switch volt-ampere (V-A) products. These optimizations then permit comparison among several switched-capacitor topologies, and comparisons of SC converters with conventional magnetic-based dc-dc converter circuits, in the context of various application settings. Significantly, the performance (based on conduction loss) of a ladder-type converter is found to be superior to that of a conventional magnetic-based converter for medium to high conversion ratios.

Review of Charge Pump Topologies for Micro Energy Harvesting Systems

“…11b) has reasonable switch and capacitor efficiency as reported in (Seeman and Sanders, 2008). The Fibonacci structure also has good current drivability in LV ranges (Gupta et al, 2013), low ripples and a good pump-up ratio (Ueno et al, 1991) due to its non-linearity and exponential nature.…”

“…As stated in (Seeman and Sanders, 2008), Series Parallel CP performs better in a capacitor limited process with impedance inversely proportional to frequency while the Dickson and Ladder CP (Fig. 11a) works best in a switch limited process (Seeman and Sanders, 2008) with frequency-independent constant current flow. Hence, the CPs either uses switches or capacitors efficiently, but not simultaneously superior in both asymptotes (Seeman and Sanders, 2008).…”

“…11 and 12 representing Ladder CP (Bender, 1994;Seeman and Sanders, 2008;Bazzini et al, 2012), Fibonacci CP (Ueno et al, 1991;Makowski and Maksimovic, 1995;Seeman and Sanders, 2008;Allasasmeh and Gregori, 2011;Gupta et al, 2013), Exponential CP (Cernea et al, 2009;Allasasmeh and Gregori, 2011) and a recently patented Tree Topology CP (Lu et al, 2010;Roy et al, 2014) respectively. As stated in (Seeman and Sanders, 2008), Series Parallel CP performs better in a capacitor limited process with impedance inversely proportional to frequency while the Dickson and Ladder CP (Fig. 11a) works best in a switch limited process (Seeman and Sanders, 2008) with frequency-independent constant current flow.…”

“…11a) works best in a switch limited process (Seeman and Sanders, 2008) with frequency-independent constant current flow. Hence, the CPs either uses switches or capacitors efficiently, but not simultaneously superior in both asymptotes (Seeman and Sanders, 2008). Recently, Bazzini et al (2012) proposes an all PMOS Double Ladder CP which lowers output resistance, R OUT(OPT) Pelliconi et al (2003) design with the i-stage pumping capacitor, C PUMP(i) = (N+1-i)/(N(N+1)C TOT (Bazzini et al, 2012) chosen to minimize R OUT (Makowski and Maksimovic, 1995).…”

“…For optimal performance, the N-th stage Fibonacci CP requires the largest capacitor nearest to V IN and the smallest capacitor to be closest to the load. (Chang and Hu, 2004;Gobbi et al, 2007;Seeman and Sanders, 2008). Fibonacci CPs (Ueno et al, 1991;Allasasmeh and Gregori, 2011;Gupta et al, 2013) and voltage doublers (Seeman and Sanders, 2008) are categorized as exponential or non-linear CPs.…”