This paper provides a perspective on progress toward realization of efficient, fully integrated dc-dc conversion and regulation functionality in CMOS platforms. In providing a comparative assessment between the inductor-based and switchedcapacitor approaches, the presentation reviews the salient features in effectiveness in utilization of switch technology and in use and implementation of passives. The analytical conclusions point toward the strong advantages of the switched-capacitor (SC) approach with respect to both switch utilization and much higher energy densities of capacitors versus inductors. The analysis is substantiated with a review of recently developed and published integrated dc-dc converters of both the inductor-based and SC types.Index Terms-Charge-pump, high power density, power supply on chip, switched-capacitor (SC) dc-dc converters. I. INTRODUCTIONT HE demand for integrated power conversion, regulation, and management functions has progressed along with advances in computing, communicating, and other integrated circuit technologies. Nevertheless, efficient integrated power conversion is now at its infancy in relation to the maturing development of the system-on-chip (SOC) functions that would be best served by such converters. Since present day multicore processors dissipate power in the range of 1 W/mm 2 , and would also ideally utilize many independently controlled voltage rails, a target benchmark is an integrated dc-dc conversion and regulation design that 1) handles about 10 W/mm 2 1 ; 2) steps down from a conveniently chosen voltage above typical CMOS core operating voltages; 3) provides high efficiency over a wide load and voltage range; 4) provides tight regulation; and 5) is highly scalable for granular implementation. Although there are now promising paths toward this set of goals, with both Manuscript

No abstract

No abstract

The traditional inductor-based buck converter has been the dominant design for step-down switched-mode voltage regulators for decades. Switched-capacitor (SC) DC-DC converters, on the other hand, have traditionally been used in lowpower (<10mW) and low-conversion-ratio (<4:1) applications where neither regulation nor efficiency is critical. However, a number of SC converter topologies are very effective in their utilization of switches and passive elements, especially in relation to the ever-popular buck converters [1,2,5]. This work encompasses the complete design, fabrication, and test of a CMOS-based switched-capacitor DC-DC converter, addressing the ubiquitous 12 to 1.5V board-mounted point-of-load application. In particular, the circuit developed in this work attains higher efficiency (92% peak, and >80% over a load range of 5mA to 1A) than surveyed competitive buck converters, while requiring less board area and less costly passive components. The topology and controller enable a wide input voltage (V IN ) range of 7.5 to 13.5V with an output voltage (V OUT ) of 1.5V. Control techniques based on feedback and feedforward provide tight regulation (30mV pp ) under worst-case load-step (1A) conditions. This work shows that SC converters can outperform buck converters, and thus the scope of SC converter applications can and should be expanded. The input voltage may range from 7.5 to 13.5V, while the converter outputs a nominal voltage of 1.5V, defined by an on-chip bandgap reference. Capacitors C 1 to C 9 are the power-train capacitors, and they are implemented with off-chip ceramic capacitors. The Dickson converter operates in 2 phases, and achieves voltage conversion through charge transfers among capacitors C 1 to C 9 [4]. Switches S 1 to S 12 are the power switches, and the phase in which they are turned on is indicated by the number in bracket next to the switch label in the figure; the switch is turned off in the other phase. Switches S 13 to S 18 are also power switches, but they may turn on in either clock phase depending on the conversion ratio of the converter. For example, in order to attain a conversion ratio of 7.5 to 1, switches S 13 and S 15 are on while switches S 14 , S 16 , S 17 , and S 18 are off during clock phase 1, and switches S 14 and S 17 are on while switches S 13 , S 15 , S 16 , and S 18 are off during clock phase 2. The timing sequence of switches S 13 to S 18 allows the converter to attain 7 different conversion ratios, ranging from 5 to 1 to 8 to 1 with half integer steps. The integrated circuit implementation, in a 0.18µm triple-well CMOS process, is sub-divided into various voltage domains to allow the usage of low-voltage transistors (blocking a maximum of 4V) to accommodate moderate V IN levels, as high as 13.5V [5]. This converter achieves regulation by adjusting its nominal conversion ratio, and by modulating the switch conductance of switches S 1,4,5 [6]. Switch conductance modulation [3] allows tight regulation for line and load variation whereas changing conversion ratio a...

No abstract