Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters

Le, Hanh-Phuc; Sanders, S.R.; Alon, Elad

doi:10.1109/jssc.2011.2159054

Cited by 373 publications

(222 citation statements)

References 17 publications

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“…The above application space sets the goals for a voltage regulator powering digital circuits. Previous work in this area [3,[8][9][10][11][12][13][14] have attempted to achieve this goal but either had limited output power ranges or displayed degraded efficiency at lower output voltages. Other works such as [15,16] have shown very high power densities but need additional fabrication steps to build the inductor in the interposer or the package substrate high power density and efficiency [17].…”

Section: P=ctotmentioning

confidence: 99%

Improvement Of Conversion Efficiency For Passive Elements Converter Load In Digital Circuits

2018

IJRTER

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Section: P=ctotmentioning

confidence: 99%

Improvement Of Conversion Efficiency For Passive Elements Converter Load In Digital Circuits

2018

IJRTER

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“…It shows the upper limit of the efficiency of any kind of SC DC-DC converters; in other words, the maximum attainable efficiency decreases as the voltage drop between the no-load voltage (V NL ) and the average load voltage (V L_up ) increases. Considering only the charge transfer, the efficiency can be defined as the ratio of the total charge delivered to the load shown in Equation (3) to the charge extracted from the input voltage source shown in Equation (2). The relationship between ΔVL_up and ΔVL_dw is determined by the ratio between Cup and Cdw, which will be derived in Equation (6).…”

Section: Charge Transfer and Loss Mechanismsmentioning

confidence: 99%

“…From Equations (2) and (3), and Figure 3b, the load current driving capability at a fixed switching Considering only the charge transfer, the efficiency can be defined as the ratio of the total charge delivered to the load shown in Equation (3) to the charge extracted from the input voltage source shown in Equation (2). The relationship between ΔVL_up and ΔVL_dw is determined by the ratio between Cup and Cdw, which will be derived in Equation (6).…”

Section: =V L_upmentioning

confidence: 99%

“…Since on-chip capacitors have a significantly higher quality factor, higher energy density, and a lower cost than on-chip inductors in the standard complementary metal-oxide-semiconductor (CMOS) process, switched-capacitor (SC)-based on-chip DC-DC converters have been receiving increased attention from both academia and industry [1][2][3][4][5].…”

Section: Introductionmentioning

confidence: 99%

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Fully Integrated on-Chip Switched DC–DC Converter for Battery-Powered Mixed-Signal SoCs

Jeon

Kim

2017

Symmetry

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This paper presents a fully integrated on-chip switched-capacitor (SC) DC-DC converter that supports a programmable regulated power supply ranging from 2.6 to 3.2 V out of a 5 V input supply. The proposed 4-to-3 step-down topology utilizes two conventional 2-to-1 step-down topologies; each of them (2-to-1_up and 2-to-1_dw) has a different flying capacitance to maximize the load current driving capability while minimizing the bottom-plate capacitance loss. The control circuits use a low power supply provided by a small internal low-drop output (LDO) connected to the internal load voltage (V L_dw ) from the 2-to-1_dw, and low swing level-shifted gate-driving signals are generated using the internal load voltage (V L_dw ). Therefore, the proposed implementation reduces control circuit and switching power consumptions. The programmable power supply voltage is regulated by means of a pulse frequency modulation (PFM) technique with the compensated two-stage operational transconductance amplifier (OTA) and the current-starved voltage controlled oscillator (VCO) to maintain high efficiency over a wide range of load currents. The proposed on-chip SC DC-DC converter is designed and simulated using high-voltage 0.35 µm bipolar, complementary metal-oxide-semiconductor (CMOS) and DMOS (BCDMOS) technology. It achieves a peak efficiency of 74% when delivering an 8 mA load current at a 3.2 V supply voltage level, and it provides a maximum output power of 48 mW (I L = 15 mA at V L_up = 3.2 V) at 70.5% efficiency. The proposed on-chip SC voltage regulator shows better efficiency than the ideal linear regulator over a wide range of output power, from 2.6 mW to 48 mW. The 18-phase interleaving technique enables the worst-case output voltage ripple to be less than 5.77% of the load voltage.

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“…On-chip MOS capacitors with density as high as 10nF/mm 2 are available in digital CMOS processes [2]. However, choosing the right topology is important.…”

Section: Introductionmentioning

confidence: 99%

A fully integrated battery-connected switched-capacitor 4:1 voltage regulator with 70% peak efficiency using bottom-plate charge recycling

Tong

Zhang

Kim

et al. 2013

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

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Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters

Cited by 373 publications

References 17 publications

Improvement Of Conversion Efficiency For Passive Elements Converter Load In Digital Circuits

Improvement Of Conversion Efficiency For Passive Elements Converter Load In Digital Circuits

Fully Integrated on-Chip Switched DC–DC Converter for Battery-Powered Mixed-Signal SoCs

A fully integrated battery-connected switched-capacitor 4:1 voltage regulator with 70% peak efficiency using bottom-plate charge recycling

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