Trivalent logic is also called as ternary logic is a promising alternative to the conventional Boolean space. In modern VLSI, CMOS technologies are invented and the die size is reducing day by day. So the complexities on the die increases resulting into the high integration on the same die size. I order to drive the logic, we have to think about the multi-valued logic cell as there are some limitations with the conventional Boolean space. Ternary logic provides simplicity and energy efficiency in digital design as the logic reduces the complexity of interconnects and chip area along with the higher density of information storage. The proposed paper presents the physical design implementation of the various ternary arithmetic circuits which involves the universal gates as T-NAND and T-NOR. The ternary arithmetic based design are aimed to achieve the low power consumption, high stability. The physical designs are implemented and simulated using the Microwind 3.5 EDA tool with CMOS 45nm technology.

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Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past three decades. However, as the technology scaling enters nanometer regime, CMOS devices are facing many serious problems such as increased leakage currents, difficulty on increase of on-current, large parameter variations, low reliability and yield, increase in manufacturing cost, and etc. To sustain the historical improvements, various innovations in CMOS materials and device structures have been researched and introduced. In parallel with those researches, various new nanoelectronic devices, so called "Beyond CMOS Devices," are actively being investigated and researched to supplement or possibly replace ultimately scaled conventional CMOS devices. While those nanoelectronic devices offer ultra-high density system integration, they are still in a premature stage having many critical issues such as high variations and deteriorated reliability. The practical realization of those promising technologies requires extensive researches from device to system architecture level. In this paper, the current researches and challenges on nanoelectronics are reviewed and critical tasks are summarized from device level to circuit design/CAD domain to better prepare for the forthcoming technologies.

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