Challenges for Nanoscale MOSFETs and Emerging Nanoelectronics

Kim, Yong-Bin

doi:10.4313/teem.2010.11.3.093

Cited by 215 publications

(80 citation statements)

References 66 publications

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“…The various leakage currents in OFF transistor are subthreshold leakage current, gateinduced drain leakage, junction leakage current, and direct tunneling current [17][18][19].…”

Section: Power Consumption In Sram-based Fpgasmentioning

confidence: 99%

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Singh¹

2017

Field - Programmable Gate Array

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The design of low-power SRAM cell becomes a necessity in today's FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power. The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low-power SRAMbased FPGA at system level, device level, and architecture levels. Finally, the chapter proposes a data-aware dynamic SRAM cell to control the power consumption in the cell. Stack effect has been adopted in the design to reduce the leakage current. The various peripheral circuits like address decoder circuit, write/read enable circuits, and sense amplifier have been modified to implement a power-efficient SRAM-based FPGA.

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“…The various leakage currents in OFF transistor are subthreshold leakage current, gateinduced drain leakage, junction leakage current, and direct tunneling current [17][18][19].…”

Section: Power Consumption In Sram-based Fpgasmentioning

confidence: 99%

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Singh¹

2017

Field - Programmable Gate Array

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“…The increase of leakage and OFF-current reduces the reliability of a circuit [20]. Massive process variation, critical power overhead, and a decrease in the gate control are other destructive challenges of MOSFET devices at the nanoscale [20]- [22]. According to Moore's law, it can be concluded that the bulk-silicon transistor should be replaced by a promising alternative device in the near future [19].…”

Section: Introductionmentioning

confidence: 99%

“…Another negative effect of miniaturization is the exponential increase of leakage current involving subthreshold voltage caused by scaling down the supply voltage and threshold voltage [19]. The increase of leakage and OFF-current reduces the reliability of a circuit [20]. Massive process variation, critical power overhead, and a decrease in the gate control are other destructive challenges of MOSFET devices at the nanoscale [20]- [22].…”

Section: Introductionmentioning

confidence: 99%

An Efficient 5-Input Exclusive-OR Circuit Based on Carbon Nanotube FETs

Zarhoun

Moaiyeri

Farahani

et al. 2014

ETRI J

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The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube fieldeffect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.Keywords: Nanotechnology, carbon nanotube fieldeffect transistor, CNTFET, high-performance circuits, CNTFET-based inverter, exclusive-OR gate, XOR gate. Manuscript received Jan. 13, 2013; revised Apr. 2, 2013; accepted Apr. 5, 2013. Ronak Zarhoun (phone: +98 2129904195, r.zarhoon@mail.sbu.ac.ir), Mohammad H. Moaiyeri (h_moaiyeri@sbu.ac.ir), and Samira S. Farahani (sa.shirinabadi@mail.sbu.ac.ir) are with the Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University, G.C., Tehran, Iran.Keivan Navi (corresponding author, navi@sbu.ac.ir, knavi@uci.edu) is with the Quantum Computing Laboratory, Shahid Beheshti University, G.C., Tehran, Iran, and is also with the Department of Electrical Engineering and Computer Science, University of California, Irvine, Irvine, CA, USA. I. IntroductionNo one can imagine today's world without the influence and power of computer technology, which dominates many aspects of people's lives, from such simple details as cell phones to such important and critical projects as those in aeronautics. All computer-based technological improvements are possible through computational functions, which are made up of precise logic gates. Such logic gates as NOT, NAND, NOR, and XOR are the main building blocks of logical functions [1], [2]. Considering these gates, the XOR gate plays a significant role in computational processors with low-power purposes and arithmetic circuits [3], [4], such as full adder cells [5], [6]-[8], parity bit generators and parity checkers [9], multipliers such as the polynomial basis multiplier [10], and comparator circuits [8], [11], [12]. High-speed XOR gates are needed for summation of partial products in multiplier circuits, and they are also used in MUX modules in arithmetic circuits [12].The most famous application of the XOR gate is in coding processes and data encryption or decryption, especially in AES (Advanced Encryption Standard) [1], which is sufficiently used in data communication. In design testing, it is used in built-in self-test structures [...

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“…To fabricate CMOS transistors into smaller and smaller size [1].It will eventually hits its limitations. Hence several alternatives have been proposed.…”

Section: Introductionmentioning

confidence: 99%