This paper presents a novel 8T SRAM cell which contains two tail transistors in the pull-down path of the respective inverter to minimize the write power consumption. The simulated results show that the proposed cell consumes about 57.87% lower power and gives faster response compared to the conventional 6T SRAM cell during a write operation. To compensate the read delay and static noise margin (SNM) losses due to the two extra tail transistors in the proposed cell, we have to enlarge the width of these two tail transistors.

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Two alternate topologies of lossless grounded inductor have been proposed using operational transresistance amplifier (OTRA). Three applications using the proposed inductors are also included. PSPice simulation and experimental results have been included to demonstrate the performance and verify the theoretical analysis.

The issue of unintentional islanding in grid interconnection still remains a challenge in grid-connected, Distributed Generation System (DGS). This study discusses the general overview of popular islanding detection methods. Because of the various Distributed Generation (DG) types, their sizes connected to the distribution networks, and, due to the concern associated with out-of-phase reclosing, anti-islanding continues to be an issue, where no clear solution exists. The passive islanding detection technique is the simplest method to detect the islanding condition which compares the existing parameters of the system having some threshold values. This study first presents an auto-ground approach, which is based on the application of three-phase, short-circuit to the islanded distribution system just to reclose and re-energize the system. After that, the data mining-decision tree algorithm is implemented on a typical distribution system with multiple DGs. The results from both of the techniques have been accomplished and verified by determining the Non-Detection Zone (NDZ), which satisfies the IEEE standards of 2 s execution time. From the analysis, it is concluded that the decision tree approach is effective and highly accurate to detect the islanding state in DGs. These simulations in detail compare the old and new methods, clearly highlighting the progress in the field of islanding detection.

Power consumption and Static noise margin (SNM) are most important parameters for memory design. The main source of power consumption in SRAM cell is due to large voltage swing on the bitlines during write operation. To reduce the power consumption and enhance the performance of the SRAM cell, we propose a Low-power fast (LPF) SRAM cell. The cell is simulated in terms of power, delay and read stability. The simulated result shows that the read and write power of the proposed cell is reduced up to 33% and 57.12% at 1.2 V (in CMOS 0.12 µm technology) respectively compared to the 6 T cell. The read SNM of the LPF cell is 2x times of the conventional cell.

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