Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset

Lin, Sheng; Kim, Yong-Bin; Lombardi, Fabrizio

doi:10.1109/tdmr.2011.2167233

Cited by 103 publications

(77 citation statements)

References 20 publications

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“…In 1.1 V and 1.2 V the SNM of [9] is better than SRAM circuits designed in this paper. In the same supply voltage, the result of RATF1 and RATF2 is better than that of [8] and [4]. Therefore, there is a trade-off between the SNM and power consumption, related to the supply voltage.…”

Section: Comparative Analysesmentioning

confidence: 96%

“…A similar scenario could repeat when the cell contains logic value of '0' (shown in Figure 9b). In cases in which the switch transistors are ON for a short time, energetic particle strikes could alter the stored value of the RATF1, RATF2, 10T [9], 11T [8], and 13T [4]. All these SRAM cells use the periodically ON/OFF feedbacks and hence they have some nodes that striking energetic particles could change the stored value of.…”

Section: Radiation Robustness In the Presence Of Single Event Upsetsmentioning

confidence: 99%

“…Consequently, the stored value of the SRAM cell will turn to a faulty logic value. This phenomenon is called single event upset (SEU) [3][4][5][6][7]. Figure 1a shows the conventional 6T SRAM cell.…”

Section: Introductionmentioning

confidence: 99%

“…In this case, the value of X1 changes from '0' to '1' and a similar scenario repeats. As SEU is a concerning issue in safety-critical applications, designing of SEU tolerant SRAM cells has been widely taken into consideration [3,4,7]. There are many noticeable factors such as node capacitance and supply voltage of transistors that affect the failure mechanism of SEUs in VLSI circuits.…”

Section: Introductionmentioning

confidence: 99%

“…There are many noticeable factors such as node capacitance and supply voltage of transistors that affect the failure mechanism of SEUs in VLSI circuits. For instance, by reducing the size of transistors and supply voltage, the sensitivity of SRAM cells to the energetic particle collisions increases [3,4]. A large amount of research has been carried out regarding SEU tolerance of SRAM cells.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology

Rajaei¹,

Asgari²,

Tabandeh³

et al. 2017

Turk J Elec Eng & Comp Sci

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Abstract:In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are proposed and evaluated. The proposed radiation hardened SRAM cells are capable of fully tolerating single event upsets (SEUs).Moreover, they show a high degree of robustness against single event multiple upsets (SEMUs). Over the previous SRAM cells, RATF1 and RATF2 offer lower area and power overhead. The Hspice simulation results through comparison with some prominent and state-of-the-art soft error tolerant SRAM cells show that our proposed robust SRAM cells have smaller area overhead (RAFT1 offers 58% smaller area than DICE), lower power delay product (RATF1 offers 231.33% and RATF2 offers 74.75% lower PDP compared with DICE), much more soft error robustness, and larger noise margins.

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Section: Comparative Analysesmentioning

confidence: 96%

Section: Radiation Robustness In the Presence Of Single Event Upsetsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology

Rajaei¹,

Asgari²,

Tabandeh³

et al. 2017

Turk J Elec Eng & Comp Sci

View full text Add to dashboard Cite

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A review on radiation‐hardened memory cells for space and terrestrial applications

Mukku¹,

Lorenzo²

2022

Circuit Theory & Apps

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Over the past four decades, single event upset (SEU) and single event multiple node upset (SEMNU) have become the major issues in the memory area.Moreover, these upsets are prone to reliability issues in space, terrestrial, military, and medical applications. This article concisely reviews different researchers and academicians who proposed resilience techniques and methods to mitigate this upset mess. In addition, we also investigated the importance of Q Crit and the impact of Q Crit on device scaling parameters in upset mechanism, probability of memory failure, and the figure of metrics for the stability of memory cells.critical charge, figure of metric, single event upset, single event multiple node upset, soft error | INTRODUCTIONTo enhance the functionality of system-on-chip (SoC), designers scale down the dimensions of the transistors. 1 According to the international technology roadmap for semiconductors (ITRS) prediction on memory size, and its processing engines on mobile type SoC, it is expected to rise by a factor of 18 between 2013 and 2025, 2,3 which is shown in Figure 1. Massive increasing the transistor count certainly increases the power consumption and degrade the mobile battery's life.Recent SoCs are embedded with static random access memory (SRAM) memories due to the faster and more reliable read/write approaches. Therefore, these SRAMs are used as cache and main memories. Moreover, SRAM memories occupy a maximum area on SoC's. 2 Hence, chip designers scale down the process technology of the memories. The problem with process technology scaling would lower the standard operating voltage, conversely, due to the process variations, memory density increases. 4 Figure 2 shows the trends of industrial standard processors and SRAM memories with various operating voltages at different technology nodes presented in ISSCC. 3 Scaling the process technology node of SRAM memories is more sensitive to transistor variations. 5 This scaling also increases the soft error rate (SER). Ibe et al 6 discuss the SER of SRAM memories in 22 nm node rises by a factor of 7 as compared with 130 nm design. On the other hand, when an electronic component is subjected to radiation, its electrical properties change due to technology node scaling, large densities, and lower operating voltages. These exposures to radiation cause temporary or permanent system breakdown.Three distinct radiation environments are feasible to define, from earth's sea level to the planet's space orbit. They are terrestrial, atmospheric, and van Allen belt radiations. The National Aeronautical Space Administration (NASA) investigated spacecraft anomalies between 1974 and 1994 space missions. 7 Among those 100 various missions, it is clear that 35% and above of anomalies are caused to spacecraft failure due to the electronic component's radiation effects. So

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A highly stable and low‐cost 12T radiation hardened SRAM cell design for aerospace application

Liu

Xie

et al. 2023

Circuit Theory & Apps

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SummaryIn this paper, a highly stable and low‐cost 12T (HSLC12T) radiation hardened static‐random‐access‐memories (SRAM) cell is proposed in 55 nm CMOS technology. Based on polarity reversal design and read/write separation structure, the proposed HSLC12T cell can recover from any single event upsets (SEUs) induced at all its sensitive nodes and even single event double‐node‐upsets (SEDNUs) induced at its internal storage node pair Q‐QN, while also having the maximum read static noise margin (RSNM) and lower static hold power, as well as excellent write speed and write‐ability. Though the HSLC12T cell exhibits a larger read delay, it has the best overall performance of all other cells. This is proven by having the highest electrical quality metric (EQM) value, thus making the proposed HSLC12T cell a better choice for aerospace applications.

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Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset

Cited by 103 publications

References 20 publications

Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology

Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology

A review on radiation‐hardened memory cells for space and terrestrial applications

A highly stable and low‐cost 12T radiation hardened SRAM cell design for aerospace application

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