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As technology size scales down toward lower 2-digit nanometer dimensions, sensitivity of CMOS circuits to radiation effects increases. Static Random Access Memories (SRAMs) that are mostly employed as high performance and high-density memories are prone to radiation induced Single Event Upsets (SEUs). Therefore, designing reliable SRAM cells have always been a serious challenge. In this article, we propose two novel SRAM cells namely RHD11 and RHD13 that provide more attractive features than their latest proposed counterparts. Simulation results show that, our proposed SRAM cells as compared with some state of the art designs have considerably higher robustness against Single Event Multiple Effects (SEMU). Moreover, they offer a sensible area overhead advantage so that, our proposed RHD11 SRAM cell has 19.9% smaller area than the prominent dual interlocked cell (DICE). The simulation results and analyses show that, our proposed SRAM cells especially the proposed RHD13 has a considerable lower failure probability among the considered recent radiation hardened SRAM cells. Index Terms-Soft error, Single Event Upset (SEU), SingleEvent Multiple Effect (SEME), SRAM cell.

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In this paper, we propose two novel soft error tolerant latch circuits namely HRPU and HRUT. The proposed latches are both capable of fully tolerating single event upsets (SEUs). Also, they have the ability of enduring single event multiple upsets (SEMUs). Our simulation results show that, both of our HRPU and HRUT latches have higher robustness against SEMUs as compared with other recently proposed radiation hardened latches. We have also explored the effects of process and temperature variations on different design parameters such as delay and power consumption of our proposed latches and other leading SEU tolerant latches. Our simulation results also show that, compared with the reference (unprotected) latch, our HRPU latch has 57% and 34% improvements in propagation delay and power delay product (PDP) respectively. In addition, process and temperature variations have least effects on HRPU in comparison with the other latches. Allowing little more delay, we designed HRUT latch that can filter single event transients (SETs). HRUT has been designed to be immune against SEUs, SEMUs and SETs with an acceptable overhead and sensitivity to process and temperature variations.

Generation of random numbers is one of the most important steps in cryptographic algorithms. High endurance, high performance and low energy consumption are the attractive features offered by the Magnetic Tunnel Junction (MTJ) devices. Therefore, they have been considered as one of the promising candidates for next-generation digital integrated circuits. In this paper, a new circuit design for true random number generation using MTJs is proposed. Our proposed circuit offers a high speed, low power and a truly random number generation. In our design, we employed two MTJs that are configured in special states. Generated random bit at the output of the proposed circuit is returned to the write circuit to be written in the relevant cell for the next random generation. In a random bitstream, all bits must have the same chance of being “0”or “1”. We have proposed a new XOR-based method in this paper to resolve this issue in multiple random generators that produce truly random numbers with a different number of ones and zeros in the output stream. The simulation results using a 45[Formula: see text]nm CMOS technology with a special model of MTJ validated the advantages offered by the proposed circuit.

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Field-programmable gate arrays (FPGA) based on static random access memory (SRAM) are more common than other types, including flash and anti-fuse because of their infinite configurability and high performance. However, following the scaling down of CMOS technology, standby power of the CMOS circuits are becoming crucial. Logic circuits based on magnetic RAM (MRAM) can be attractive replacement for the SRAM-based logics thanks to their zero leakage and CMOS compatibilities. Furthermore, in FPGA design, using MRAM logic instead of SRAM logic results in some more advantages including non-volatility and high radiation reliability. In this paper, effects of radiation induced soft errors on MRAM-based FPGAs (MFPGA) is taken into account. Soft error tolerance of the previous MFPGAs are discussed and a new MFPGA structure is proposed. It is shown that, the proposed non-volatile, low power and high speed MFPGA is highly robust against radiation induced soft errors. It also is shown that, the proposed MFPGA offering a high radiation robustness does not incur a considerable design overhead comparing with the other similar MFPGAs.