A new SRAM cell design using CNTFETs

Lin, Sheng; Kim, Yong-Bin; Lombardi, Fabrizio

doi:10.1109/socdc.2008.4815599

Cited by 60 publications

(49 citation statements)

References 6 publications

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“…The CNTs under the gate region are undoped or intrinsic to have semiconducting behavior and can be controlled by the gate input voltage [26]. The dielectric layer under the gate is deposited on the undoped CNTs (in the middle), and the metal gate layer covers it [18]. Single-wall CNT partitions between the gate and the drain and source are heavily doped to provide low resistors in a serial state whenever the transistor is in its active mode, as shown in Fig. 1 [18], [32].…”

Section: Cntfet Reviewmentioning

confidence: 99%

“…The dielectric layer under the gate is deposited on the undoped CNTs (in the middle), and the metal gate layer covers it [18]. Single-wall CNT partitions between the gate and the drain and source are heavily doped to provide low resistors in a serial state whenever the transistor is in its active mode, as shown in Fig. 1 [18], [32]. The CNTFETs switch between active mode and inactive mode by manipulating the electrical potential of the gate.…”

Section: Cntfet Reviewmentioning

confidence: 99%

“…In reports on CNTFET fabrication, it was declared that a near-ballistic [23] or even ballistic transportation can be gained from an intrinsic CNT under low voltage with an approximately 1 micrometer mean free path needed for elastic scattering to obtain efficient improvement in performance [32]- [34]. The fabrication of single-wall CNT (SWCNT) transistors was reported in [18], [35]. An SWCNT, which is made up of a single cylinder of a rolled graphene sheet, can either be metallic or semiconducting [19], [21], [36].…”

Section: Cntfet Reviewmentioning

confidence: 99%

“…The scaling down of technology has closely reflected Moore's law. As the length of physical gates reaches the nanoscale, different destructive effects, such as short channel effects, affect the current-voltage characteristics of the MOSFET family, which limits the miniaturization of the feature size of this family [2], [17], [18]. Another negative effect of miniaturization is the exponential increase of leakage current involving subthreshold voltage caused by scaling down the supply voltage and threshold voltage [19].…”

Section: Introductionmentioning

confidence: 99%

“…There are three types of CNTFET: The first type is the MOSFET-like CNTFET (includes the p-type CNTFET [P-CNTFET] and n-type CNTFET [N-CNTFET]), which operates in a unipolar fashion; The second type is the Schottky barrier (SB) CNTFET, which demonstrates ambipolar characteristics [31] but is not proper for ultra high-performance applications because of the SB element; The third type of CNTFET, suitable for ultra lowpower applications, is the band-to-band tunneling CNTFET and has significantly low current in its active mode [23]. The CNTFET has relatively low off-current whenever the transistor is inactive; in other words, when the CNTFET is off, leakage power consumption is very low [18]. CNTFETs have similar structure and electrical characteristics to MOSFETs, which facilitates the exploitation and reuse of previous MOSFETbased architectures and fabrication processes [21].…”

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confidence: 99%

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An Efficient 5-Input Exclusive-OR Circuit Based on Carbon Nanotube FETs

Zarhoun

Moaiyeri

Farahani

et al. 2014

ETRI J

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The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube fieldeffect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.Keywords: Nanotechnology, carbon nanotube fieldeffect transistor, CNTFET, high-performance circuits, CNTFET-based inverter, exclusive-OR gate, XOR gate. Manuscript received Jan. 13, 2013; revised Apr. 2, 2013; accepted Apr. 5, 2013. Ronak Zarhoun (phone: +98 2129904195, r.zarhoon@mail.sbu.ac.ir), Mohammad H. Moaiyeri (h_moaiyeri@sbu.ac.ir), and Samira S. Farahani (sa.shirinabadi@mail.sbu.ac.ir) are with the Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University, G.C., Tehran, Iran.Keivan Navi (corresponding author, navi@sbu.ac.ir, knavi@uci.edu) is with the Quantum Computing Laboratory, Shahid Beheshti University, G.C., Tehran, Iran, and is also with the Department of Electrical Engineering and Computer Science, University of California, Irvine, Irvine, CA, USA. I. IntroductionNo one can imagine today's world without the influence and power of computer technology, which dominates many aspects of people's lives, from such simple details as cell phones to such important and critical projects as those in aeronautics. All computer-based technological improvements are possible through computational functions, which are made up of precise logic gates. Such logic gates as NOT, NAND, NOR, and XOR are the main building blocks of logical functions [1], [2]. Considering these gates, the XOR gate plays a significant role in computational processors with low-power purposes and arithmetic circuits [3], [4], such as full adder cells [5], [6]-[8], parity bit generators and parity checkers [9], multipliers such as the polynomial basis multiplier [10], and comparator circuits [8], [11], [12]. High-speed XOR gates are needed for summation of partial products in multiplier circuits, and they are also used in MUX modules in arithmetic circuits [12].The most famous application of the XOR gate is in coding processes and data encryption or decryption, especially in AES (Advanced Encryption Standard) [1], which is sufficiently used in data communication. In design testing, it is used in built-in self-test structures [...

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Section: Cntfet Reviewmentioning

confidence: 99%

Section: Cntfet Reviewmentioning

confidence: 99%

Section: Cntfet Reviewmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

See 3 more Smart Citations

An Efficient 5-Input Exclusive-OR Circuit Based on Carbon Nanotube FETs

Zarhoun

Moaiyeri

Farahani

et al. 2014

ETRI J

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Design of an ultralow power CNTFET based 9T SRAM with shared BL and half select free techniques

Patel

Malik

Gupta

2018

Int J Numerical Modelling

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In this paper, we propose a new design of high-performance ultralow power carbon nanotube field effect transistor (CNTFET)-based nine-transistor static random access memory (SRAM) cell and its implementation using shared bitline (BL) and half-select free techniques. Simulations of the 9T SRAM design, using CNTFET compact model, have presented merits over the silicon-complementary-metal oxide semiconductor (CMOS) SRAM cell in terms of leakage current, power consumption, and stability. Uses of the half-select free technique eliminate the conflict between read and write operations and shared BL technique offers reduced physical layout area and enhanced data access speed. Further, uses of the increased number of tubes or say CNT array in the CNTFET device increases the probability of functionality (>95%) with a high yield SRAM cell.

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